AD9772EB Analog Devices, AD9772EB Datasheet - Page 13

• Manufacturer Part Number: AD9772EB
• Description: 14-Bit/ 160 MSPS TxDAC+ with 2x Interpolation Filter
• Manufacturer: Analog Devices

“Zero Stuffing” Option Description
As shown in Figure 25, a “zero” or null in the frequency re-
sponses (after interpolation and DAC reconstruction) occurs at
the final DAC update rate (i.e., 2 f
inherent sin(x)/x roll-off response. In baseband applications, this
roll-off in the frequency response may not be as problematic
since much of the desired signal energy remains below f
and the amplitude variation is not as severe. However, in direct
IF applications interested in extracting an image above f
this roll-off may be problematic due to the increased passband
amplitude variation as well as the reduced signal level of the
higher images.
For instance, if the digital data into the AD9772 represented a
baseband signal centered around f
f
would experience only a 0.18 dB amplitude variation over its
passband with the “1st image” occurring at 7/4 f
of attenuation relative to the fundamental. However, if the high-
pass filter response was selected, the AD9772 would now pro-
duce pairs of images at [(2N + 1) f
0, 1 . . .. Note, due to the DAC’s sin(x)/x response, only the
lower or upper sideband images centered around f
useful although they would be attenuated by –2.1 dB and
–6.54 dB respectively as well as experience a passband ampli-
tude roll-off of 0.6 dB and 1.3 dB.
To improve upon the passband flatness of the desired image
and/or to extract higher images (i.e., 3 f
the “zero-stuffing” option should be employed by bringing the
MOD1 pin HIGH. This option increases the effective DAC
update rate by another factor of two since a “midscale” sample
(i.e., 10 0000 0000 0000) is inserted after every data sample
originating from the 2 interpolation filter. A digital multiplexer
switching at a rate of 4 f
output and a data register containing the “midscale” data sample is
used to implement this option as shown in Figure 24. Hence,
the DAC output is now forced to return to its differential mid-
scale current value (i.e., IOUTA–IOUTB 0 mA) after recon-
structing each data sample from the digital filter.
REV. 0
DATA
Figure 25. Effects “Zero-Stuffing” on DAC’s Sin(x)/x
Response
/10, the reconstructed baseband signal out of the AD9772
–10
–20
–30
–40
0
BASEBAND
0
REGION
0.5
"ZERO-STUFFING"
WITHOUT
1
DATA
FREQUENCY –
1.5
between the interpolation filter’s
2
DATA
DATA
DATA
f
"ZERO-STUFFING"
DATA
/4 with a passband of
2.5
) due to the DAC’s
]
DATA
WITH
f
3
DATA
DATA
f
FUNDAMENTAL
DATA
/4 where N =
3.5
with 17 dB
may be
DATA
DATA
4
/2
/2,
)
–13–
The net effect is to increase the DAC update rate such that the
“zero” in the sin(x)/x frequency response now occurs at 4
f
shown in Figure 25. Note, if the 2 interpolation filter’s high
pass response is also selected, this action can be modeled as a
“1/4 wave” digital mixing process since this is equivalent to
digitally mixing the impulse response of the low-pass filter with
a square wave having a frequency of exactly f
It is important to realize that the “zero stuffing” option by itself
does not change the location of the images but rather their signal
level, amplitude flatness and relative weighting. For instance, in
the previous example, the passband amplitude flatness of the
lower and upper sideband images centered around f
improved to 0.14 dB and 0.24 dB respectively, while the signal
level has changed to –6.5 dBFS and –7.5 dBFS. The lower or
upper sideband image centered around 3
amplitude flatness of 0.77 dB and 1.29 dB with signal levels of
approximately –14.3 dBFS and –19.2 dBFS.
PLL CLOCK MULTIPLIER OPERATION
The Phase Lock Loop (PLL) clock multiplier circuitry along
with the clock distribution circuitry can produce the neces-
sary internally synchronized 1 , 2 , and 4 clocks for the edge
triggered latches, 2 interpolation filter, “zero stuffing” multi-
plier, and DAC. Figure 26 shows a functional block diagram of
the PLL clock multiplier, which consists of a phase detector, a
charge pump, a voltage controlled oscillator (VCO), a prescaler,
and digital control inputs/outputs. The clock distribution
circuitry generates all the internal clocks for a given mode of
operation. The charge pump and VCO are powered from
PLLVDD while the differential clock input buffer, phase detec-
tor, prescaler and clock distribution circuitry are powered from
CLKVDD. To ensure optimum phase noise performance from
the PLL clock multiplier and clock distribution circuitry,
PLLVDD and CLKVDD must originate from the same clean
analog supply.
CLKCOM
DATA
CLKVDD
Figure 26. Clock Multiplier with PLL Clock Multiplier
Enabled
OUT1
along with a corresponding reduction in output power as
PLLLOCK
DISTRIBUTION
CLOCK
CLK+
+
CLOCK CONTROL
CLK–
–
PRESCALER
DETECTOR
EXT/INT
PHASE
AD9772
CHARGE
PUMP
f
VCO
DATA
DATA
AD9772
will exhibit an
(i.e., f
DATA
COM
VDD
LPF
PLL
PLL
DAC
are
+2.7V TO
+3.6V
392
/4).
1.0 F