L64780 LSI Logic Corporation, L64780 Datasheet - Page 60

• Manufacturer Part Number: L64780
• Description: Dvb-t Cofdm Demodulator Technical Manual 2/00
• Manufacturer: LSI Logic Corporation

4-8
TPS_INFO_CHANGE
Register Descriptions
The Sync change event is visible through the signal
SYNC CHANGE (see
ing Registers Address Line
least one of the following synchronizations has changed
during the demodulation:
TPS Change Interrupt
A valid TPS structure has been received that differs from
the current mode of the DTTV demodulator. This interrupt
does not occur if the only change is in the frame number.
The TPS_INFO_CHANGE bit is initially reset to 0 (no
interrupt). If this bit is set to 1, an interrupt is generated.
The TPS_INFO_CHANGE bit is set to 1 only when the
received error-free (BCH-correct) TPS is different from
the last TPS information stored in the TPS registers. This
bit is only reset by a microprocessor read access. The
TPS_INFO_CHANGE bit is evaluated every COFDM
frame, and it is visible through the TPS_INFO_CHANGE
signal (see
The Frame_Sync_OK bit is set to 1 when the frame
synchronization is reached and reset to 0 when the
frame synchronization is lost. The Frame_Sync_OK
bit is visible through the Performance Monitoring
register.
The Freq_Sync_OK bit is set to 1 when the demodu-
lator is frequency locked and reset to 0 when the fre-
quency synchronization is not yet reached or lost. The
Freq_Sync_OK bit is visible through Performance
Monitoring Register 1.
The Start_Sync_OK bit is set to 1 when the timing
block has properly determined the start of the FFT; it
is reset to 0 when this is lost. Start_Sync_OK bit is
visible through Performance Monitoring Register 1.
The Clock_Sync_OK bit is set to 1 when the sampling
frequency is properly locked; it is reset to 0 when sync
is not reached. Clock_Sync_OK is visible through Per-
formance Monitoring register 1.
The TPS_Sync_OK bit is set to 1 when the TPS
frame is error free; it is reset to 0 when the frame is
corrupted. The TPS_Sync_OK bit is visible through
Performance Monitoring Register 1.
Section 4.3, “TPS
Section 4.6, “Performance Monitor-
0x16”) and occurs when at
Registers”).
R 0