L64767 LSI Logic Corporation, L64767 Datasheet - Page 16

• Manufacturer Part Number: L64767
• Description: Smatv Qam Encoder
• Manufacturer: LSI Logic Corporation

Microprocessor Interface Signals
16
TRST
This section describes the microprocessor interface signals of the L64767.
ADR[3:0]
AS_N
CS_N
DATA[7:0]
DTACK_N
L64767 SMATV QAM Encoder
JTAG Test Reset
When HIGH, this level-sensitive data signal resets the
JTAG unit. In default normal operational mode, TRST is
LOW.
Address for Internal Registers
This is a level-sensitive, 4-bit address bus the L64767
uses along with the 8-bit data bus DATA[7:0], a read/write
strobe (READ), a chip select strobe (CS_N), and an
address strobe (AS_N) to read and write internal
registers. The address lines are used to select among
internal registers.
Address Strobe
This is an active LOW address strobe input signal. It
latches the address on the ADR[3:0] bus on the falling
edge.
Chip Select
This is an active LOW chip select strobe input signal.
During a read cycle, CS_N must be LOW to access the
on-chip data registers. The controller can latch the data
from the L64767 with the rising edge of CS_N. During a
write cycle, CS_N must go active LOW prior to data being
valid from the controller to the L64767. After the data has
met the minimum setup time, CS_N HIGH will strobe the
data. There is a minimum write time to allow for internal
synchronization.
Data Bus [7:0]
This is a level-sensitive data signal. The bidirectional data
bus is used for input when writing data to the chip, and
as output when the chip is read. When not being read or
written, the data lines are 3-stated.
Data Acknowledge
This is an active LOW output signal indicating that the
transaction on the data bus is completed.
Bidirectional
Output
Input
Input
Input
Input