ADP3168 Analog Devices, ADP3168 Datasheet - Page 17

• Manufacturer Part Number: ADP3168
• Description: 4-Phase Synchronous Buck Controller
• Manufacturer: Analog Devices

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4
C
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
One can also use some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
The first thing is to select the total amount of ceramic capaci-
tance. This is based on the number and type of capacitor to be
used. The best location for ceramics is inside the socket, with
12 to 18 of size 1206 being the physical limit. Others can be
placed along the outer edge of the socket as well.
Combined ceramic values of 200 µF to 300 µF are recom-
mended, usually made up of multiple 10 µF or 22 µF capacitors.
Select the number of ceramics and then find the total ceramic
capacitance (C
Next, there is an upper limit imposed on the total amount of
bulk capacitance (C
voltage stepping of the output (voltage step V
error of V
capacitance for load release for a given maximum load step ∆I
To meet the conditions of these expressions and transient re-
sponse, the ESR of the bulk capacitor bank (R
than two times the droop resistance, R
than C
specification and may require the use of a smaller inductor or
more phases (and may have to increase the switching frequency
to keep the output ripple the same).
OUT
C
C
where
SELECTION
nK
x
x
X(MAX)
(
(
MIN
MAX
L
2
R
ERR
O
)
2
)
K
, the system does not meet the VID on-the-fly
) and a lower limit based on meeting the critical
≥
≤
×
⎛
⎜
⎜
⎝
Z
=
).
n
V
V
1
VID
×
V
n
L
R
⎛
⎜
⎜
⎝
X
×
O
×
) when one considers the VID on-the-fly
V
Δ
×
V
ERR
⎛
⎜
⎜
⎜
⎝
I
V
V
O
VID
1
⎞
⎟
⎟
⎠
+
−
⎛
⎜
⎜
⎝
C
t
v
z
V
⎞
⎟
⎟
⎠
V
VID
V
×
O
nKR
. If the C
L
O
V
⎞
⎟
⎟
⎠
X
) should be less
2
in time t
X(MIN)
−
1
⎞
⎟
⎟
⎟
⎠
−
is larger
C
V
z
with
(12)
(13)
Rev. B | Page 17 of 24
O
:
For our example, 23 10 µF 1206 MLC capacitors (C
were used. The VID on-the-fly step change is 250 mV in 150 µs
with a setting error of 2.5 mV. Solving for the bulk capacitance
yields
Using eight 820 µF A1-Polys with a typical ESR of 8 mΩ each
yields C
One last check should be made to ensure that the ESL of the
bulk capacitors (L
frequency transient spike. This is tested using
In this example, L
which satisfies this limitation. If the L
capacitor bank is too large, the number of capacitors must be
increased.
One should note that for this multimode control technique, all
ceramic designs can be used as long as the conditions of
Equations 11, 12, and 13 are satisfied.
where k = 4.6
C
C
⎛
⎜
⎜
⎜
⎝
=
L
L
x
x
x
x
23
(
(
1
X
MIN
MAX
≤
≤
+
= 6.56 mF with an R
9 .
C
230
⎛
⎜ ⎜
⎝
)
)
z
mF
150
≤
≤
×
µF
⎛
⎜ ⎜
⎝
3
R
3
µs
×
X
×
X
×
600
) is low enough to limit the initial high
4
is 375 pH for the eight A1-Polys capacitors,
1
×
(
250
1
600
6 .
3 .
1
3 .
2
nH
5 .
m
×
m
mV
nH
V
Ω
(
Ω
×
1
×
3 .
×
)
60
×
×
2
3
1
X
m
250
=
5 .
600
×
A
= 1.0 mΩ.
Ω
389
4
V
)
6 .
2
mV
nH
−
×
×
pH
X
230
1
1
of the chosen bulk
5 .
3 .
V
m
µF
Ω
×
⎞
⎟ ⎟
⎠
⎞
⎟ ⎟
⎠
=
2
. 5
−
ADP3168
92
1
Z
⎞
⎟
⎟
⎟
⎠
= 230 µF)
−
mF
230
(14)
µF