S2053 AMCC (Applied Micro Circuits Corp), S2053 Datasheet - Page 12

• Manufacturer Part Number: S2053
• Description: Bicmos Lvpecl Clock Generator Fibre Channel And Gigabit Ethernet Transceiver
• Manufacturer: AMCC (Applied Micro Circuits Corp)

12
S2053
Table 11. S2053 Receiver Timing
Notes:
1. All LVTTL/CMOS AC measurements are assumed to have the output load of 10pF.
2. All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels
(.8V or 2.0V).
T
T
Parameters
Duty Cycle
Input Jitter
RCR ,
T
SDR ,
Tolerance
DR ,
T
LOCK
T
T
T
T
T
3
4
5
6
7
T
T
T
RCF
DF
SDF
Table 10. S2053 Transmitter Timing
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or
output data levels (.8V or 2.0V).
T
Transmitter Output Jitter Allocation
Parameters
SDR ,
T
J RMS
T
RBC0 to RBC1 skew
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
RBC0, RBC1 rise and fall time
Data Output rise and fall time
Serial data input rise and fall
Data acquisition lock time @
<1.0625Gb/s
RBC0/RBC1 Duty Cycle
Input data eye opening
allocation at receiver input
for BER 1E–12
T
T
T
T
DJ
1
2
1
2
T
SDF
Description
Serial data output
deterministic jitter (p-p)
Data setup w.r.t. REFCLKP/N
Data hold w.r.t. REFCLKP/N
Data setup w.r.t. TREFCLK
Data hold w.r.t. TREFCLK
Serial data rise and fall
Serial data output random
jitter (RMS)
Table 9. S2053 Performance Summary
*
Description
O
S
B
A
R
W
r e
y
c
e
p
o
10% lock range, nominal frequency is per FC-PH standard.
e t
q
e f
r e
d r
a i
i u
e r
t a
c l
c
t i s
P
w
o l
n
n i
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
o l
d i
a
o i
k c
c
g
e
a r
k c
h t
n
F
p
c
i T
e r
m
p
r e
o l
r e
m
q
k c
o i
t e
u
e
o i
d
e
r e
d
n
y c
40%
30%
Min
7.5
3.0
1.5
2.5
—
—
—
—
2
*
Min
1.5
1.0
1.5
1.0
—
—
—
1
1
8 .
8
60%
300
2
8.5
3.0
3.0
2.4
2
Max
2
1
—
0 .
5
300
100
0
5
Max
5
0
—
—
—
—
20
0
0
0
0 .
0
S
S
S
S
S
2
2
2
2
2
0
0
0
0
0
bit time
5
5
5
5
5
Units
Units
ns
ns
ns
ns
ps
ps
ps
3
3
3
3
3
ns
ns
ns
ns
ns
ns
ns
ps
1
1
s
0
9 .
9
0
2
1
6
4 .
6
5
4
0
2
2 .
0
1
1
5 .
5
See note.
See note.
20% to 80%, tested on a sample basis.
RMS, tested on a sample basis.
Measured with K28.7 pattern at
1250 Mbps.
Peak-to-peak, tested on a sample basis.
Measured with K28.5
1250 Mbps.
Tested on a sample basis.
1.0625 GHz Mode
1.0625 GHz Mode
1.250 GHz Mode
1.250 GHz Mode
Measured from .8V to 2.0V.
Measured from .8V to 2.0V.
20% to 80%. (See Figure 10.)
8B/10B IDLE pattern sample basis
As specified in Fibre Channel FC–PH
standard eye diagram jitter mask.
U
M
M
B
i n
b
n
n
n
H
s t i
Conditions
t i
s
s
s
s t
z
s /
Conditions
pattern at