S2053 AMCC (Applied Micro Circuits Corp), S2053 Datasheet

S2053

Manufacturer Part Number

S2053

Description

Bicmos Lvpecl Clock Generator Fibre Channel And Gigabit Ethernet Transceiver

Manufacturer

AMCC (Applied Micro Circuits Corp)

Datasheet

1.S2053.pdf (15 pages)

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FEATURES

APPLICATIONS

High-speed data communications

Figure 1. System Block Diagram

PRELIMINARY

DEVICE SPECIFICATION

BiCMOS LVPECL CLOCK GENERATOR

FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER

• Functionally compliant with ANSI X3T11 Fibre

• Transmitter incorporates phase-locked loop

• Receiver PLL configured for clock and data

• 1250 and 1062 Mb/s operation

• 10-bit parallel high drive LVTTL compatible

• 900mW typical power dissipation

• +3.3V power supply

• Low-jitter serial LVPECL compatible interface

• Lock detect

• Local loopback

• 64 PQFP package

• Fibre Channel framing performed by receiver

• Continuous downstream clocking from receiver

• Drives 30m of Twinax cable directly

• Low jitter LVPECL reference clock input option

• Workstation

• Frame buffer

• Switched networks

• Data broadcast environments

• Proprietary extended backplanes

• RAID drives

• Mass storage devices

FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER

Channel physical and transmission protocol

standards and IEEE 802.3z Gigabit Ethernet

Applications

(PLL) providing clock synthesis from low-speed

reference

recovery

interface

Controller

Ethernet

Gigabit

Open Fiber

S2053

Control

S2036

(OFC)

Optical

GENERAL DESCRIPTION

The S2053 transmitter and receiver chip is designed

to perform high-speed serial data transmission over

fiber optic or coaxial cable interfaces conforming to

the requirements of the ANSI X3T11 Fibre Channel

specification and the IEEE 802.3z Gigabit Ethernet.

The chip runs at 1250.0, and 1062.5 Mbit/s data rates

with associated 10-bit data word.

The S2053 is similar to the AMCC S2052. The S2053

provides the option of either a single ended LVTTL or

a differential LVPECL reference clock input and high

drive LVTTL outputs. The differential LVPECL refer-

ence clock input provides the lowest transmitter output

jitter solution. The high drive LVTTL outputs allow

longer trace lengths or connectors to be used be-

tween the S2053 and the Media Access Controller.

The chip performs parallel-to-serial and serial-to-

parallel conversion and framing for block-encoded

data. The transmitter’s on-chip PLL synthesizes the

high-speed clock from a low-speed reference. The

receiver’s on-chip PLL synchronizes directly to

incoming digital signal to receive the data stream.

The transmitter and receiver each support differential

LVPECL-compatible I/O for fiber optic component

interfaces, to minimize crosstalk and maximize data

integrity. Local loopback mode is provided for system

diagnostics.

Figure 1 shows a typical configuration incorporating

the chip, which is compatible with AMCC’s S2036

Open Fiber Control (OFC) device.

Optical

Open Fiber

S2053

Control

S2036

(OFC)

Controller

Ethernet

Gigabit

S2053

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