IDT82V2082 Integrated Device Technology, Inc., IDT82V2082 Datasheet - Page 15

• Manufacturer Part Number: IDT82V2082
• Description: 2Ch T1/J1/E1 Short Haul/long Haul Liu
• Manufacturer: Integrated Device Technology, Inc.

DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
MONT2
MONT1
GNDT1
GNDT2
VDDR1
VDDR2
GNDR1
GNDR2
GNDIO
VDDT1
VDDT2
VDDIO
GNDD
GNDA
Name
VDDD
VDDA
TRST
TMS
TCK
TDO
RST
THZ
TDI
Pullup
Pullup
Pullup
Type
O
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
I
-
-
Pin No.
7,40
8,39
18
19
21
20
61
80
64
77
68
73
65
76
31
29
69
72
1
2
3
4
5
MONT2: Receive Monitor gain select for channel 2
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
MONT1: Receive Monitor gain select for channel 1
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
RST: Hardware Reset
The chip is forced to reset state if a low signal is input on this pin for more than 100ns.
THZ: Transmitter Driver High Impedance Enable
This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while a high
level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not affected by
this signal.
TRST: JTAG Test Port Reset
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure determin-
istic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal pull-
up resistor.
TCK: JTAG Test Clock
This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while the
data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-state devices
contained in the test logic will retain their state indefinitely.
TDO: JTAG Test Data Output
This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test logic.
The data on TDO is clocked out of the device on the falling edge of TCK.
TDI: JTAG Test Data Input
This pin is used for loading instructions and data into the test logic and has an internal pull-up resistor. The data on TDI is
clocked into the device on the rising edge of TCK.
3.3 V I/O power supply
I/O ground
3.3 V power supply for transmitter driver
Analog ground for transmitter driver
Power supply for receive analog circuit
Analog ground for receive analog circuit
3.3V digital core power supply
Digital core ground
Analog core circuit power supply
Analog core circuit ground
Power Supplies and Grounds
JTAG Signals
15
Description
TEMPERATURE RANGES
INDUSTRIAL