IDT82V2082 Integrated Device Technology, Inc., IDT82V2082 Datasheet
IDT82V2082
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IDT82V2082 Summary of contents
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... Single rail/dual rail system interfaces - B8ZS/HDB3/AMI line encoding/decoding DESCRIPTION: The IDT82V2082 can be configured as a dual channel T1 Line Interface Unit. In receive path, an Adaptive Equalizer is integrated to remove the distortion introduced by the cable attenuation. The IDT82V2082 also performs clock/data recovery, AMI/B8ZS/HDB3 line decoding and detects and reports the LOS conditions ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT FUNCTIONAL BLOCK DIAGRAM LOSn LOS/AIS Detector RCLKn B8ZS/ Jitter RDn/RDPn HDB3/AMI Attenuator CVn/RDNn Decoder PRBS Detector Remote Loopback IBLC Detector TCLKn B8ZS/ Jitter TDn/TDPn HDB3/AMI Attenuator TDNn Decoder PRBS Generator IBLC ...
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... DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT TABLE OF CONTENTS TABLE OF CONTENTS 1 IDT82V2082 PIN CONFIGURATIONS .......................................................................................... 8 2 PIN DESCRIPTION ....................................................................................................................... 9 3 FUNCTIONAL DESCRIPTION .................................................................................................... 17 3.1 CONTROL MODE SELECTION ....................................................................................... 17 3.2 T1/E1/J1 MODE SELECTION .......................................................................................... 17 3.3 TRANSMIT PATH ............................................................................................................. 17 3.3.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17 3.3.2 ENCODER ............................................................................................................. 17 3.3.3 PULSE SHAPER .................................................................................................... 17 3.3.3.1 Preset Pulse Templates .......................................................................... 17 3.3.3.2 LBO (Line Build Out) ............................................................................... 18 3 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.8.4.3 Automatic Remote Loopback .................................................................. 32 3.9 ERROR DETECTION/COUNTING AND INSERTION ...................................................... 33 3.9.1 DEFINITION OF LINE CODING ERROR ............................................................... 33 3.9.2 ERROR DETECTION AND COUNTING ................................................................ 33 3.9.3 BIPOLAR VIOLATION ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT LIST OF TABLES Table-1 Pin Description ................................................................................................................ 9 Transmit Waveform Value For E1 75 Ω ........................................................................ 19 Table-2 Transmit Waveform Value For E1 120 Ω ...................................................................... 19 Table-3 Table-4 Transmit Waveform ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-47 INTM1: Interrupt Masked Register 1 ............................................................................. 50 Table-48 INTES: Interrupt Trigger Edge Select Register ............................................................. 51 Table-49 STAT0: Line Status Register 0 (real time status monitor)............................................. 52 Table-50 STAT1: Line ...
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... DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT LIST OF FIGURES Figure-1 Block Diagram ................................................................................................................. 2 Figure-2 IDT82V2082 TQFP80 Package Pin Assignment ............................................................ 8 Figure-3 E1 Waveform Template Diagram .................................................................................. 17 Figure-4 E1 Pulse Template Test Circuit ..................................................................................... 18 Figure-5 DSX-1 Waveform Template .......................................................................................... 18 Figure-6 T1 Pulse Template Test Circuit ..................................................................................... 18 Figure-7 Receive Path Function Block Diagram .......................................................................... 23 Figure-8 Transmit/Receive Line Circuit ...
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... RTIP1 67 VDDR1 68 VDDA REF 71 GNDA 72 73 VDDR2 RTIP2 74 RRING2 75 GNDR2 76 77 GNDT2 78 TTIP2 79 TRING2 80 VDDT2 Figure-2 IDT82V2082 TQFP80 Package Pin Assignment IDT82V2082 8 INDUSTRIAL TEMPERATURE RANGES VDDIO 40 GNDIO 39 TCLK1 38 TDP1 / TD1 37 TDN1 36 RCLK1 35 RDP1 / RD1 34 RDN1 / CV1 33 LOS1 32 VDDD 31 MCLK 30 GNDD ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 2 PIN DESCRIPTION Table-1 Pin Description Name Type Pin No. TTIP1 Analog 63 TTIPn TTIP2 Output 78 These pins are the differential line driver outputs and can be set to high ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type Pin No. RD1/RDP1 O 34 RDn: Receive Data output for Channel 1~2 RD2/RDP2 26 In single rail mode, this pin outputs NRZ data. The data ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type Pin No. MODE1 I 9 MODE[1:0]: operation mode of control interface select MODE0 10 The level on this pin determines which control mode is used ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type Pin No. SCLK I 46 SCLK: Shift Clock In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type Pin No. SDO O 43 SDO: Serial Data Output In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type Pin No A5: Address Bus bit5 In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface. In ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type Pin No. MONT2 I 18 MONT2: Receive Monitor gain select for channel 2 In hardware control mode with ternary interface, this pin selects the receive ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-1 Pin Description (Continued) Name Type Pin No IC: Internal Connection Internal Use. This pin should be left open when in normal operation IC: Internal ...
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... FUNCTIONAL DESCRIPTION 3.1 CONTROL MODE SELECTION The IDT82V2082 can be configured by software or by hardware. The software control mode supports Serial Control Interface, Motorola non-Mul- tiplexed Control Interface and Intel non-Multiplexed Control Interface. The Control mode is selected by MODE1 and MODE0 pins as follows: Control Interface mode ...
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... Time (ns) Figure-5 DSX-1 Waveform Template TTIPn IDT82V2082 TRINGn Note 100 Ω ± 5% LOAD Figure-6 T1 Pulse Template Test Circuit For J1 applications, the PULS[3:0] (TCF1, 05H...) should be set to ‘0111’. Table-14 lists these values. 3.3.3.2 LBO (Line Build Out) To prevent the cross-talk at the far end, the output of TTIPn/TRINGn could be attenuated before transmission for long haul applications ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT The following tables give all the sample data based on the preset pulse templates and LBOs in detail for reference. For preset pulse templates and LBOs, scaling up/down against the pulse ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-5 Transmit Waveform Value For T1 133~266 ft Sample 0011011 1000011 2 0101110 1000010 3 0101100 1000001 4 0101010 0000000 5 0101001 0000000 6 0101000 0000000 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-9 Transmit Waveform Value For J1 0~655 ft Sample 0010111 1000010 2 0100111 1000001 3 0100111 0000000 4 0100110 0000000 5 0100101 0000000 6 0100101 0000000 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO Sample 0000000 0101100 2 0000000 0101110 3 0000000 0110000 4 0000000 0110001 5 0000001 0110010 6 0000011 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.3.5 TRANSMIT PATH POWER DOWN The transmit path can be powered down individually by setting the T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are turned into ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT • Line X B • T Line X Note: 1. Common decoupling capacitor 2. Cp 0-560 (pF D8, Motorola - MBR0540T1; In hardware control mode, TERMn, ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.4.3 ADAPTIVE EQUALIZER The adaptive equalizer can remove most of the signal distortion due to intersymbol interference caused by cable attenuation. It can be enabled or disabled by setting EQ_ON bit ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.4.10 G.772 NON-INTRUSIVE MONITORING In applications using only one channel, channel 1 can be configured to monitor the data received or transmitted in channel 2. The MONT[1:0] bits (GCF, 20H) determine ...
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... RDn/RDPn 128 Bits De-jittered Data RDNn 3.5.2 JITTER ATTENUATOR PERFORMANCE The performance of the Jitter Attenuator in the IDT82V2082 meets the R ITU-T I.431, G.703, G.736-739, G.823, G.824, ETSI 300011, ETSI TBR12/ De-jittered Clock 13, AT&T TR62411 specifications. Details of the Jitter Attenuator perfor- RCLKn mance is shown in Characteristics ...
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... In long haul mode, the value of Q can be selected by LOS[4:0] bit (RCF1, 0AH...), while P=Q the LOS level detect hysteresis). The LOS[4:0] default value is 10101 (-46 dB). When the chip is configured by hardware, the LOS detect level is fixed if the IDT82V2082 operates in long haul mode -46dB (E1) and -38dB (T1 ). /J1 • ...
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... AIS DETECTION The Alarm Indication Signal can be detected by the IDT82V2082 when the Clock & Data Recovery unit is enabled. The status of AIS detection is reflected in the AIS_S bit (STAT0, 16H...). In T1/J1 applications, the criteria for declaring/clearing AIS detection are in compliance with the ANSI Table-19 AIS Condition ITU G ...
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... TRANSMIT AND DETECT INTERNAL PATTERNS The internal patterns (All Ones, All Zeros, PRBS/QRSS pattern and Activate/Deactivate Loopback Code) will be generated and detected by IDT82V2082. TCLKn is used as the reference clock by default. MCLK can also be used as the reference clock by setting the PATT_CLK bit (MAINT0, 0CH...) to ‘1’. ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT LOS/AIS LOSn Detection RCLKn B8ZS/ RDn/RDPn HDB3/AMI CVn/RDNn Decoder B8ZS/ TCLKn HDB3/AMI TDn/TDPn Encoder TDNn LOS/AIS LOSn Detection B8ZS/ RCLKn Jitter RDn/RDPn HDB3/AMI Attenuator CVn/RDNn Decoder TCLKn B8ZS/ Jitter HDB3/AMI TDn/TDPn ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.8.4 INBAND LOOPBACK When PATT[1:0] bits (MAINT0, 0CH...) are set to ‘11’, the correspond- ing channel is configured in Inband Loopback mode. In this mode, an unframed activate/Deactivate Loopback Code is ...
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... DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.9 ERROR DETECTION/COUNTING AND INSERTION 3.9.1 DEFINITION OF LINE CODING ERROR The following line encoding errors can be detected and counted by the IDT82V2082: • Received Bipolar Violation (BPV) Error: In AMI coding, when two consecutive pulses of the same polarity are received, a BPV error is declared. • ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT • Manual Report Mode In Manual Report Mode, the internal Error Counter starts to count the received errors when the CNT_MD bit (MAINT6, 12H...) is set to ‘0’. When there is ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.11 MCLK AND TCLK 3.11.1 MASTER CLOCK (MCLK) MCLK is an independent, free-running reference clock. MCLK is 1.544 MHz for T1/J1 applications and 2.048 MHz in E1 mode. This reference clock ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.12 MICROCONTROLLER INTERFACES The microcontroller interface provides access to read and write the reg- isters in the device. The chip supports serial microcontroller interface and two kinds of parallel microcontroller interface: ...
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... DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 3.13 INTERRUPT HANDLING All kinds of interrupt of the IDT82V2082 are indicated by the INT pin. When the INT_PIN[0] bit (GCF, 20H) is ‘0’, the INT pin is open drain active low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits (GCF, 20H) are ‘ ...
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... PROGRAMMING INFORMATION 4.1 REGISTER LIST AND MAP The IDT82V2082 registers can be divided into Global Registers and Local Registers. The operation on the Global Registers affects both of the two channels while the operation on Local Registers only affects the spe- cific channel. For different channel, the address of Local Register is differ- ent ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-24 Per Channel Register List and Map Address (hex) Register R/W CH1 CH2 Transmit and receive termination register 02 22 TERM R/W Jitter attenuation control register 03 23 JACF R/W Transmit ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2 REGISTER DESCRIPTION 4.2.1 GLOBAL REGISTERS Table-25 ID: Device Revision Register (R, Address = 00H) Symbol Bit Default ID[7:0] 7-0 00H Table-26 RST: Reset Register (W, Address = 01H) Symbol Bit ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.2 TRANSMIT AND RECEIVE TERMINATION REGISTER Table-29 TERM: Transmit and Receive Termination Configuration Register (R/W, Address = 02H, 22H) Symbol Bit Default - 7-6 00 T_TERM[2:0] 5-3 000 R_TERM[2:0] 2-0 000 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.4 TRANSMIT PATH CONTROL REGISTERS Table-31 TCF0: Transmitter Configuration Register 0 (R/W, Address = 04H, 24H) Symbol Bit Default - 7-5 000 T_OFF 4 0 TD_INV 3 0 TCLK_SEL 2 0 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-33 TCF2: Transmitter Configuration Register 2 (R/W, Address = 06H, 26H) Symbol Bit Default - 7-6 00 SCAL[5:0] 5-0 100001 Table-34 TCF3: Transmitter Configuration Register 3 (R/W, Address = 07H, 27H) ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.5 RECEIVE PATH CONTROL REGISTERS Table-36 RCF0: Receiver Configuration Register 0 (R/W, Address = 09H, 29H) Symbol Bit Default - 7-5 000 R_OFF 4 0 RD_INV 3 0 RCLK_SEL 2 0 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-37 RCF1: Receiver Configuration Register 1 (R/W, Address= 0AH, 2AH) Symbol Bit Default - 7 0 EQ_ON LOS[4:0] 4:0 10101 Reserved = 0: Receive equalizer off ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-38 RCF2: Receiver Configuration Register 2 (R/W, Address = 0BH, 2BH) Symbol Bit Default - 7-6 00 SLICE[1:0] 5-4 01 UPDW[1:0] 3-2 10 MG[1:0] 1-0 00 4.2.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-40 MAINT1: Maintenance Function Control Register 1 (R/W, Address= 0DH, 2DH) Symbol Bit Default - 7-4 0000 ARLP 3 0 RLP 2 0 ALP 1 0 DLP 0 0 Table-41 MAINT2: ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-43 MAINT4: Maintenance Function Control Register 4 (R/W, Address = 10H, 30H) Symbol Bit Default RIBLBA[7:0] 7-0 (000)00001 Defines the user-programmable receive Inband loopback activate code. The default selection is 00001. ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.7 INTERRUPT CONTROL REGISTERS Table-46 INTM0: Interrupt Mask Register 0 (R/W, Address = 13H, 33H) Symbol Bit Default EQ_IM 7 1 IBLBA_IM 6 1 IBLBD_IM 5 1 PRBS_IM 4 1 TCLK_IM ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-47 INTM1: Interrupt Masked Register 1 (R/W, Address = 14H, 34H) Symbol Bit Default DAC_OV_IM 7 1 JAOV_IM 6 1 JAUD_IM 5 1 ERR_IM 4 1 EXZ_IM 3 1 CV_IM 2 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-48 INTES: Interrupt Trigger Edge Select Register (R/W, Address = 15H, 35H) Symbol Bit Default EQ_IES 7 0 IBLBA_IES 6 0 IBLBD_IES 5 0 PRBS_IES 4 0 TCLK_IES 3 0 DF_IES ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.8 LINE STATUS REGISTERS Table-49 STAT0: Line Status Register 0 (real time status monitor) (R, Address = 16H, 36H) Symbol Bit Default EQ_S 7 0 IBLBA_S 6 0 IBLBD_S 5 0 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-49 STAT0: Line Status Register 0 (real time status monitor) (Continued) (R, Address = 16H, 36H) Symbol Bit Default AIS_S 1 0 LOS_S 0 0 Table-50 STAT1: Line Status Register 1 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 4.2.9 INTERRUPT STATUS REGISTERS Table-51 INTS0: Interrupt Status Register 0 (R, Address = 18H, 38H) (this register is reset and relevant interrupt request is cleared after a read) Symbol Bit Default ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-52 INTS1: Interrupt Status Register 1 (R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read) Symbol Bit Default DAC_OV_IS 7 0 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 5 HARDWARE CONTROL PIN SUMMARY Table-55 Hardware Control Pin Summary Pin No. Symbol TQFP 9 MODE1 MODE[1:0]: Operation mode of Control interface select (global control) 10 MODE0 00= Hardware interface 01= ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-55 Hardware Control Pin Summary (Continued) Pin No. Symbol TQFP 46 PATT11 PATTn[1:0]: Transmit test pattern select (per channel control) 45 PATT10 In hardware control mode, these pins select the transmit ...
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... DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 6 IEEE STD 1149.1 JTAG TEST ACCESS PORT The IDT82V2082 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction regis- ters plus a Test Access Port (TAP) controller. Control of the TAP is per- ...
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... Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. The normal path between IDT82V2082 logic and the I/O pins is maintained. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-58 TAP Controller State Description STATE Test Logic Reset In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-58 TAP Controller State Description (Continued) STATE Update-IR The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK. ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 7 TEST SPECIFICATIONS Table-59 Absolute Maximum Rating Symbol VDDA, VDDD Core Power Supply VDDIO I/O Power Supply VDDT1-2 Transmit Power Supply VDDR1-2 Receive Power Supply Input Voltage, Any Digital Pin Input ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-61 Power Consumption Symbol Parameter E1, 3 Ω Load E1, 3.3 V, 120 Ω Load 3 T1, 3.3 V, 100 Ω Load J1, 3.3 V, 110 Ω Load 1.Maximum ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-63 E1 Receiver Electrical Characteristics Symbol Parameter Receiver sensitivity Short haul with cable loss@1024kHz: Long haul with cable loss@1024kHz: Analog LOS level Short haul Long haul Allowable consecutive zeros before LOS ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-64 T1/J1 Receiver Electrical Characteristics Symbol Parameter receiver sensitivity Short haul with cable loss@772kHz: Long haul with cable loss@772kHz: Analog LOS level Short haul Long haul Allowable consecutive zeros before LOS ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-65 E1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes E1, 75 Ω load E1, 120 Ω load Vo-s Zero (space) level E1, 75 Ω load E1, 120 Ω load Transmit ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-66 T1/J1 Transmitter Electrical Characteristics Symbol Vo-p Output pulse amplitudes Vo-s Zero (space) level Transmit amplitude variation with supply Difference between pulse sequences for 17 consecutive pulses (T1.102) TPW Output Pulse ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-67 Transmitter and Receiver Timing Characteristics Symbol Parameter MCLK frequency E1: T1/J1: MCLK tolerance MCLK duty cycle Transmit path TCLK frequency E1: T1/J1: TCLK tolerance TCLK Duty Cycle t1 Transmit Data ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT TCLKn TDn/TDPn TDNn RCLKn RDPn/RDn (RCLK_SEL = 0 software mode) (RCLKE = 0 hardware mode) RDNn/CVn RDPn/RDn (RCLK_SEL = 1 software mode) (RCLKE = 1 hardware mode) RDNn/CVn Table-68 Jitter Tolerance ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Figure-25 E1 Jitter Tolerance Performance Figure-26 T1/J1 Jitter Tolerance Performance 70 INDUSTRIAL TEMPERATURE RANGES ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-69 Jitter Attenuator Characteristics Parameter Jitter Transfer Function Corner (-3dB) Frequency Jitter Attenuator E1: (G.736 400 Hz @ 100 kHz T1/J1: (Per AT&T pub.62411) ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Figure-27 E1 Jitter Transfer Performance Figure-28 T1/J1 Jitter Transfer Performance 72 INDUSTRIAL TEMPERATURE RANGES ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-70 JTAG Timing Characteristics Symbol t1 TCK Period t2 TMS to TCK setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 8 MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS 8.1 SERIAL INTERFACE TIMING Table-71 Serial Interface Timing Characteristics Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT 8.2 PARALLEL INTERFACE TIMING Table-72 Non-Multiplexed Motorola Read Timing Characteristics Symbol Read Cycle Time tRC tDW Valid DS Width tRWV Delay from DS to Valid Read Signal tRWH R ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-73 Non-Multiplexed Motorola Write Timing Characteristics Symbol tWC Write Cycle Time tDW Valid DS Width Delay from DS to Valid Write Signal tRWV tRWH R Hold Time tAV Delay ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-74 Non-Multiplexed Intel Read Timing Characteristics Symbol Parameter tRC Read Cycle Time tRDW Valid RD Width Delay from RD to Valid Address tAV tAH Address to RD Hold Time tPRD RD ...
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DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT Table-75 Non-Multiplexed Intel Write Timing Characteristics Symbol tWC Write Cycle Time tWRW Valid WR Width Delay from WR to Valid Address tAV tAH Address to WR Hold Time tDV Delay from ...
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... XX X Process/ Temperature Range for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com* The IDT logo is a registered trademark of Integrated Device Technology, Inc. 79 TEMPERATURE RANGES Blank Industrial (-40 °C to +85 °C) Thin Quad Flatpack (TQFP, PN80) PF 82V2082 Long Haul/Short Haul LIU for Tech Support: 408-330-1552 email:TELECOMhelp@idt ...