S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet - Page 361

• Manufacturer Part Number: S1D13704
• Description: LCD Controller
• Manufacturer: Epson Electronics America, Inc.

Epson Research and Development
Vancouver Design Center
3.3 MC68K #1 Interface Mode
Interfacing to the Motorola MC68328 ‘Dragonball’ Microprocessor
Issue Date: 01/02/12
The MC68K #1 Interface Mode can be used to interface to the MC68328 microprocessor
if the previously mentioned, multiplexed, bus signals will not be used for other purposes.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
• The address inputs AB1 through AB15, and the data bus DB0 through DB15, connect
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
• A0 and WE1# are the enables for the low-order and high-order bytes, respectively, to be
• RD/WR# is the read/write signal that is driven low when the CPU writes to the
• WAIT# is a signal which is output from the S1D13704 to the host CPU that indicates
• The Bus Status (BS#) signal indicates that the address on the address bus is valid. This
• The WE0# signal is not used in the bus interface for MC68K #1 and must be tied high
S1D13704. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock.
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
IO or memory address space.
driven low when the host CPU is reading or writing data to the S1D13704. These must
be generated by external decode hardware based upon the control outputs from the host
CPU.
S1D13704 and is driven high when the CPU is doing a read from the S1D13704. This
signal must be generated by external decode hardware based upon the control output
from the host CPU.
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the S1D13704 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the S1D13704 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete.
signal must be generated by external decode hardware based upon the control outputs
from the host CPU.
(tied to IO V
DD
).
X26A-G-007-03
S1D13704
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