S1D13704 Epson Electronics America, Inc., S1D13704 Datasheet
S1D13704
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S1D13704 Summary of contents
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... S1D13704 Embedded Memory Color LCD Controller S1D13704 TECHNICAL MANUAL Document Number: X26A-Q-001-05 Copyright © 2001, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13704 X26A-Q-001-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 2002/09/17 ...
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... Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 http://www.epson.com.tw/ Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/ S1D13704 X26A-Q-001-05 ...
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... Page 4 S1D13704 X26A-Q-001-05 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center TECHNICAL MANUAL Issue Date: 2002/09/17 ...
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... The S1D13704 is a color/monochrome LCD graphics controller with an embedded 40K Byte SRAM display buffer. The high integration of the S1D13704 provides a low cost, low power, single chip solution to meet the require- ments of embedded markets such as Office Automation equipment, Mobile Communications devices, and Palm- size PCs where board size and battery life are major concerns. Products requiring a “ ...
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... GRAPHICS S1D13704 SYSTEM BLOCK DIAGRAM CPU CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: • S1D13704 Technical Manual • S5U13704 Evaluation Boards • Windows CE Display Driver • CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division ...
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... S1D13704 Embedded Memory LCD Controller Hardware Functional Specification Document Number: X26A-A-001-06 Copyright © 1998, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13704 X26A-A-001-06 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 02/02/01 ...
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... Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . 22 5.4 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 Bus Interface Timing 7.1.1 SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1.2 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1.3 Motorola M68K #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . 30 Hardware Functional Specification Issue Date: 02/02/01 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . Page 3 S1D13704 X26A-A-001-06 ...
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... Software Power Save Mode 13.2 Hardware Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . .85 13.3 Power Save Mode Function Summary 13.4 Panel Power Up/Down Sequence 13.5 Turning Off BCLK Between Accesses . . . . . . . . . . . . . . . . . . . . .87 13.6 Clock Requirements 14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 15 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 S1D13704 X26A-A-001 .88 Epson Research and Development Vancouver Design Center ...
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... Table 12-1: Default and Alternate SwivelView Mode Comparison . . . . . . . . . . . . . . . . . . 84 Table 13-1: Power Save Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 13-2: Software Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 13-3: Hardware Power Save Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 13-4: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 13-5: S1D13704 Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Hardware Functional Specification Issue Date: 02/02/01 List of Tables Page 5 ...
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... Page 6 S1D13704 X26A-A-001-06 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 02/02/01 ...
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... Figure 7-24: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Figure 7-25: 12-Bit TFT/D-TFD Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 7-26: TFT/D-TFD A.C. Timing Figure 8-1: Screen-Register Relationship, Split Screen Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization Figure 11-1: 2-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . 73 Hardware Functional Specification Issue Date: 02/02/01 List of Figures Page 7 S1D13704 X26A-A-001-06 ...
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... Figure 11-6: 4-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . .77 Figure 11-7: 16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . .78 Figure 11-8: 256-Level Color Mode Look-Up Table Architecture .79 Figure 12-1: Relationship Between The Screen Image and the Image Refreshed by S1D13704 . . . .80 Figure 12-2: Relationship Between The Screen Image and the Image Refreshed by S1D13704 . . . .82 Figure 13-1: Panel On/Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 Figure 14-1: Mechanical Drawing QFP14 ...
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... Products requiring a “Portrait” display can take advantage of the Swivelview™ (90° Hardware Rotate) feature of the S1D13704. Virtual and Split Screen are just some of the display modes supported. The above features, combined with the Operating System independence of the S1D13704, make it the ideal solution for a wide variety of applica- tions. Hardware Functional Specification ...
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... Example resolutions: 640x480 at a color depth of 1 bpp 640x240 at a color depth of 2 bpp 320x240 at a color depth of 4 bpp 240x160 at a color depth of 8 bpp S1D13704 X26A-A-001-06 Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date: 02/02/01 ...
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... GPIO[4:1] are available if upper LCD data pins (FPDAT[11:8]) are not required for TFT/D-TFD support or Hardware Video Invert. • IO Operates from 3.0 volts to 5.5 volts • Core operates from 3.0 volts to 3.6 volts. 2.7 Package • 80 pin QFP14 package. Hardware Functional Specification Issue Date: 02/02/01 CLK = CLKI or CLK = CLKI/2 Page 11 S1D13704 X26A-A-001-06 ...
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... Figure 3-2: Typical System Diagram (SH-3 Bus) S1D13704 X26A-A-001-06 . Oscillator CS# AB[15:0] DB[15:0] WE1# S1D13704 BS# RD/WR# RD# WE0# WAIT# BCLK RESET# . Oscillator CS# AB[15:0] DB[15:0] WE1# S1D13704 BS# RD/WR# RD# WE0# WAIT# BCLK RESET# Epson Research and Development Vancouver Design Center FPDAT[7:0] D[7:0] FPSHIFT FPSHIFT 8-bit FPFRAME FPFRAME LCD FPLINE FPLINE Display DRDY MOD ...
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... WAIT# BCLK RESET# . Oscillator CS# AB[15:0] DB[15:0] WE1# S1D13704 BS# RD/WR# RD# WE0# WAIT# BCLK RESET# Page 13 FPDAT[3:0] D[3:0] FPSHIFT FPSHIFT 4-bit FPFRAME FPFRAME LCD FPLINE FPLINE Display DRDY MOD LCDPWR FPDAT[7:0] D[7:0] FPSHIFT FPSHIFT 8-bit FPFRAME FPFRAME LCD FPLINE FPLINE Display DRDY MOD LCDPWR S1D13704 X26A-A-001-06 ...
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... S1D13704 X26A-A-001-06 . Oscillator BS# CS# AB[15:0] DB[15:0] FPDAT[11:0] S1D13704 WE0# WE1# RD RD/WR# WAIT# BCLK RESET# . Oscillator BS# CS# AB[15:0] DB[15:0] WE0# S1D13704 RD# WE1# WAIT# BCLK RESET# Epson Research and Development Vancouver Design Center D[11:0] FPSHIFT FPSHIFT 12-bit FPFRAME FPFRAME TFT FPLINE FPLINE Display DRDY DRDY LCDPWR FPDAT[8:0] D[8:0] FPSHIFT ...
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... The Sequence Controller controls data flow from the Memory Controller through the Look- Up Table and to the LCD Interface. It also generates memory addresses for display refresh accesses. Hardware Functional Specification Issue Date: 02/02/01 20k x 16-bit SRAM Memory Power Save Controller Clocks Look-Up Table Sequence Controller Memory Clock Pixel Clock Page 15 LCD LCD I/F S1D13704 X26A-A-001-06 ...
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... The LCD Interface performs frame rate modulation for passive LCD panels. It also generates the correct data format and timing control signals for various LCD and TFT/D-TFD panels. 4.1.6 Power Save Power Save contains the power save mode circuitry. S1D13704 X26A-A-001-06 Epson Research and Development Vancouver Design Center Hardware Functional Specification ...
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... Note Package type: 80 pin surface mount QFP14 Hardware Functional Specification Issue Date: 02/02/01 S1D13704 Figure 5-1: Pinout Diagram Page 17 40 VSS 39 FPFRAME 38 FPLINE 37 FPDAT0 36 FPDAT1 35 FPDAT2 34 FPDAT3 33 FPDAT4 32 FPDAT5 31 FPDAT6 30 FPDAT7 29 IOVDD 28 FPSHIFT 27 VSS 26 FPDAT8 25 FPDAT9 24 FPDAT10 23 FPDAT11 22 GPIO0 21 COREVDD S1D13704 X26A-A-001-06 ...
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... DB[15:0] I/O 13, 14, 15, 16, 17, 18, 19 S1D13704 X26A-A-001-06 RESET# Cell State This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs system address bit 0 (A0). • For MC68K #1, this pin inputs the lower data strobe (LDS#). • ...
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... See “Host Bus Interface Pin Mapping” for summary. This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs the RD/WR# signal. The S1D13704 needs this signal for early decode of the bus cycle. • For MC68K #1, this pin inputs the R/W# signal. ...
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... I/O O, FPDAT11 23 I/O FPFRAME O 39 S1D13704 X26A-A-001-06 RESET# Cell State This pin has multiple functions. • For SH-3/SH-4 mode, this pin inputs the read signal (RD#). • For MC68K #1, this pin must be tied • For MC68K #2, this pin inputs the bus size bit 1 (SIZ1). ...
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... See “LCD Interface Pin Mapping” for summary. Pin # Driver 51 C Input Clock RESET# Cell State These inputs are used to configure the S1D13704 - see As set by Summary of Configuration Options on page 22. C hardware Must be connected directly This pin has multiple functions - see REG[03h] bit 2. CS/ Input • ...
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... Host Bus Interface Pin Mapping S1D13704 SH-3 Pin Names AB[15:1] A[15:1] AB0 A0 DB[15:0] D[15:0] WE1# WE1# CS# CSn# BCLK CKIO BS# BS# RD/WR# RD/WR# RD# RD# WE0# WE0# WAIT# WAIT# RESET# RESET# S1D13704 X26A-A-001-06 Power On/Reset State 1 Active low (On) LCDPWR polarity CNF2 CNF1 CNF0 BS ...
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... LD0 R2 D1 LD1 R1 D2 LD2 R0 D3 LD3 G2 D4 UD0 G1 D5 UD1 G0 D6 UD2 B2 D7 UD3 B1 GPIO1 GPIO1 B0 GPIO2 GPIO2 GPIO2 GPIO3 GPIO3 GPIO3 GPIO4/ GPIO4/ HW Video HW Video GPIO4 Invert Invert . DD X26A-A-001-06 Page 23 12-bit S1D13704 ...
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... V T+ CMOS Schmitt inputs Negative-going Threshold V T- CMOS Schmitt inputs I Input Leakage Current IZ C Input Pin Capacitance IN HR Pull Down Resistance PD S1D13704 X26A-A-001-06 Table 6-1: Absolute Maximum Ratings V - 0 0 -65 to 150 260 for 10 sec. max at lead ...
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... BID Hardware Functional Specification Issue Date: 02/02/01 Table 6-4: Output Specifications Condition Min I = 3mA 6mA 12mA -1 0 MAX Page 25 Typ Max Units 0 S1D13704 X26A-A-001-06 ...
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... RDY# D[15:0] Hi-Z (write) D[15:0] Hi-Z (read) Note The SH-4 Wait State Control Register for the area in which the S1D13704 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK). S1D13704 X26A-A-001-06 = 3.3V ± 10 for all inputs must be < ...
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... BCLK Between Accesses” on page 87 Hardware Functional Specification Issue Date: 02/02/01 Table 7-1: SH-4 Timing Parameter CKIO after BS# (write cycle) Min Max Units 0 50 MHz 1/f CKIO 1.5T CKIO S1D13704 X26A-A-001-06 Page 27 ...
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... CSn# WEn# RD# t12 Hi-Z WAIT# D[15:0] Hi-Z (write) D[15:0] Hi-Z (read) Note The SH-3 Wait State Control Register for the area in which the S1D13704 resides must be set to a non-zero value. S1D13704 X26A-A-001- t13 t14 Figure 7-2: SH-3 Bus Timing Epson Research and Development Vancouver Design Center t5 t11 ...
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... Issue Date: 02/02/01 Table 7-2: SH-3 Bus Timing Parameter CKIO after BS# (write cycle) One Software WAIT State Required a Min Max Units 0 50 MHz 1/f CKIO 1.5T CKIO S1D13704 X26A-A-001-06 Page 29 ...
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... UDS#, LDS# falling edge to D[15:0] driven (read cycle) t11 D[15:0] valid to DTACK# falling edge (read cycle) t12 UDS#, LDS# rising edge to D[15:0] high impedance Note CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 87 S1D13704 X26A-A-001-06 VALID t11 t10 ...
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... Issue Date: 02/02/01 VALID t10 VALID Figure 7-4: M68K #2 Timing (MC68030) Table 7-4: M68K #2 Timing (MC68030) Parameter Hi-Z t9 Hi-Z VALID t11 Hi-Z Min Max 0 33 1/f CLK CLK 26 T CLK CLK X26A-A-001-06 Page 31 Units MHz S1D13704 ...
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... WE0#, WE1# high (write cycle) or RD0#, RD1# high (read cycle) to WAIT# t10 high impedance t11 WAIT# high to WE0#, WE1#, RD0#, RD1# high Note BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off BCLK Between Accesses” on page 87 S1D13704 X26A-A-001-06 VALID Figure 7-5: Generic #1 Timing Table 7-5: Generic #1 Timing ...
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... Hardware Functional Specification Issue Date: 02/02/01 VALID Figure 7-6: Generic #2 Timing Table 7-6: Generic #2 Timing Parameter t2 t4 VALID t7 t6 VALID t10 t11 Min Max 0 50 1/f BCLK BCLK BCLK X26A-A-001-06 Page 33 Hi-Z Hi-Z Units MHz S1D13704 ...
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... PWL t Input Clock Fall Time (10 Input Clock Rise Time (10% - 90%) r Note When CLKI is > 25MHz the Input Clock Divide bit (REG[02h] bit 4) must be set to 1. S1D13704 X26A-A-001- PWH PWL CLKI Figure 7-7: Clock Input Requirements for CLKI ...
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... Input Clock Pulse Width Low (BCLK) PWL t Input Clock Fall Time (10 Input Clock Rise Time (10% - 90%) r Hardware Functional Specification Issue Date: 02/02/ PWH PWL BCLK Parameter 1/f Min Max Units 0 50 MHz ns CLKI S1D13704 X26A-A-001-06 Page 35 ...
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... Symbol REG[03h] to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY t1 active FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to t2 LCDPWR Note Where T S1D13704 X26A-A-001- Figure 7-9: LCD Panel Power On/Reset Timing Parameter is the period of FPFRAME and T FPFRAME Epson Research and Development Vancouver Design Center ...
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... Issue Date: 02/02/ Inactive Active t4 t5 Inactive Active Figure 7-10: Power Down/Up Timing Table 7-9: Power Down/Up Timing Parameter Inactive Active t7 t6 Inactive Active Min Typ Max 127 X26A-A-001-06 Page 37 Units Frame Frame Frame Frame Frame Frame Frame S1D13704 ...
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... For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1 Figure 7-11: Single Monochrome 4-Bit Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13704 X26A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 HDP 1-1 ...
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... Hardware Functional Specification Issue Date: 02/02/ t14 t7 Parameter t11 t10 t12 t13 1 2 Min Typ Max note 2 (note 1) 9 note note 4 note 5 t14 + X26A-A-001-06 Page 39 Units S1D13704 ...
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... For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1 Figure 7-13: Single Monochrome 8-Bit Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13704 X26A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-1 ...
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... Hardware Functional Specification Issue Date: 02/02/ t14 t11 t7 t12 t13 1 Min Typ note 2 9 note note 4 note 5 t14 + Page 41 t9 t10 2 Max Units (note S1D13704 X26A-A-001-06 ...
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... FPDAT5 1-B1 FPDAT4 1-R2 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13704 X26A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-G2 1-B3 1-B2 1-R4 1-R3 ...
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... Hardware Functional Specification Issue Date: 02/02/ t14 t7 Parameter t11 t10 t12 t13 1 2 Min Typ Max note 2 9 note note 4 note 5 t14 + 0.5 1 0.5 0.5 0.5 0.5 23 X26A-A-001-06 Page 43 Units (note S1D13704 ...
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... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-17: Single Color 8-Bit Panel Timing (Format 1) VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13704 X26A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-R1 1-G1 ...
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... Parameter t11 t10 t12 t13 1 2 Min Typ Max Units note 2 (note 1) 9 note 3 9 note 4 note 5 note 6 note 7 t14 + X26A-A-001-06 Page S1D13704 ...
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... Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7-19: Single Color 8-Bit Panel Timing (Format 2) VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13704 X26A-A-001-06 VDP LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 HDP 1-B3 1-G6 ...
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... Hardware Functional Specification Issue Date: 02/02/ t14 Parameter t11 t10 t12 t13 1 2 Min Typ Max Units note 2 (note 1) 9 note note 4 note 5 t14 + X26A-A-001-06 Page S1D13704 ...
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... Example timing for a 640x480 panel Figure 7-21: Dual Monochrome 8-Bit Panel Timing VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13704 X26A-A-001-06 VDP LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 HDP 1-1 ...
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... Hardware Functional Specification Issue Date: 02/02/ t14 Parameter t11 t10 t12 t13 1 2 Min Typ Max Units note 2 (note 1) 9 note note 5 note 6 t14 + X26A-A-001-06 Page S1D13704 ...
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... FPDAT3 FPDAT2 FPDAT1 FPDAT0 * Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel VDP = Vertical Display Period VNDP = Vertical Non-Display Period HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period S1D13704 X26A-A-001-06 VDP LINE 1/241 LINE 2/242 HDP 1-G 2 1-G6 1-B7 1-R1 1-B3 1-R 5 1-R4 1-B2 ...
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... Hardware Functional Specification Issue Date: 02/02/ t14 Parameter t11 t10 t12 t13 1 2 Min Typ Max note 2 (note 1) 9 note note 5 note 6 t14 + X26A-A-001-06 Page 51 Units S1D13704 ...
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... Vertical Non-Display Period VNDP1 = Vertical Non-Display Period 1 VNDP2 = Vertical Non-Display Period 2 HDP = Horizontal Display Period HNDP = Horizontal Non-Display Period HNDP1= Horizontal Non-Display Period 1 HNDP2= Horizontal Non-Display Period 2 S1D13704 X26A-A-001-06 VNDP 2 HNDP 2 1-1 1-2 1-1 1-2 1-1 1-2 Figure 7-25: 12-Bit TFT/D-TFD Panel Timing = (REG[06h] bits 1-0, REG[05h] bits 7- Lines ...
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... Line Pulse Line Pulse DRDY Shift Pulse FPDAT[11:0] Note: DRDY is used to indicate the first pixel Hardware Functional Specification Issue Date: 02/02/01 t9 t12 t7 t17 t11 Figure 7-26: TFT/D-TFD A.C. Timing t8 t6 t14 t13 t16 639 640 t10 X26A-A-001-06 Page 53 t15 S1D13704 ...
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... min = [((REG[06h] bits 1-0, REG[05h] bits 7-0)+1) + (REG[0Ah] bits 6-0)] Lines 4. t10min = [((REG[04h] bits 6-0)+ t14min = [((REG[04h] bits 6-0)+ t15min = [(REG[07h] bits 4- 16 t17min = [(REG[08h] bits 4-0) - (REG[07 16] Ts S1D13704 X26A-A-001-06 Parameter Min 1 0.5 ...
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... Epson Research and Development Vancouver Design Center 8 Registers 8.1 Register Mapping The S1D13704 registers are located in the upper 32 bytes of the 64K byte S1D13704 address range. The registers are accessible when CS and AB[15:0] are in the range FFE0h through FFFFh. 8.2 Register Descriptions Unless specified otherwise, all register bits are reset to 0 during power up. ...
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... These bits select the display data format. See Table 8-1: “Panel Data Format” below. TFT/STN Color/Mono Dual/Single REG[01h] bit 7 REG[01h] bit 5 REG[01h] bit (don’t care) S1D13704 X26A-A-001-06 Table 8-1: Panel Data Format Data Width Data Width Bit 1 Bit 0 REG[01h] bit 1 REG[01h] bit ...
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... Gray shade 4 bit-per-pixel 1 reserved 0 2 Colors 1 bit-per-pixel 1 4 Colors 2 bit-per-pixel 0 16 Colors 4 bit-per-pixel 1 256 Colors 8 bit-per-pixel Display Modes 0 MClk = PClk/8 1 bit-per-pixel 1 MClk = PClk/4 2 bit-per-pixel 0 MClk = PClk/2 4 bit-per-pixel 1 MClk = PClk 8 bit-per-pixel X MClk = PClk Page 57 Software Video Invert S1D13704 X26A-A-001-06 ...
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... When this bit = 1, Inverse video mode is selected. When this bit = 0, standard video mode is selected. See Table 8-4: “Inverse Video Mode Select Options” below. Note Video data is inverted after the Look-Up Table. Hardware Video Invert Enable S1D13704 X26A-A-001-06 Table 8-4: Inverse Video Mode Select Options Software Video Invert (Passive Panels ...
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... Hardware Software Software Power Save Power Save Power Save Enable Bit 1 Bit 0 GPIO0 Status/Control GPIO0 Operation REG[19h] bit 0 X GPIO0 Input reads pin status (high impedance) 0 GPIO0 Output = 0 1 GPIO0 Output = 1 Hardware Power Save X Input (active high) S1D13704 X26A-A-001-06 Page 59 ...
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... REG[06h] bits 1-0 This 10-bit register determines the vertical resolution of the panel. This register must be programmed with a value calculated as follows: VerticalPanelSizeRegister 3FFh is the maximum value of this register for a vertical resolution of 1024 lines. S1D13704 X26A-A-001-06 Horizontal Horizontal Panel Size Bit Panel Size Bit ...
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... FPLINE Start FPLINE Start Position Bit 2 Position Bit 1 Position Bit Read/Write Horizontal Horizontal Horizontal Non-Display Non-Display Non-Display Period Bit 2 Period Bit 1 Period Bit Read/Write FPFRAME FPFRAME FPFRAME Start Position Start Position Start Position Bit 2 Bit 1 X26A-A-001-06 Page 61 Bit 0 S1D13704 ...
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... These bits determine the word address of the start of Screen 1 in landscape modes or the byte address of the start of Screen 1 in SwivelView modes. REG[0Dh] bit 7 Screen 1 Start Address Bit 15 This bit is for SwivelView mode only and has no effect in Landscape mode. S1D13704 X26A-A-001-06 Vertical Non- Vertical Non- Display ...
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... Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Bit 2 Bit 1 Bit 0 Read/Write Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Bit 10 Bit 9 Bit 8 Read/Write Memory Memory Memory Address Address Address Offset Bit 2 Offset Bit 1 Offset Bit 0 X26A-A-001-06 Page 63 S1D13704 ...
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... Screen 1 Vertical Size Bits [9:0] REG[13h] bits 7-0 This register is used to implement the Split Screen feature of the S1D13704. These bits determine the height (in lines) of Screen 1. On reset this register is set to 0h. In landscape modes, if this register is programmed with a value, n, where n is less than the Vertical Panel Size (REG[06h], REG[05h]), then lines the panel contain Screen 1 and lines n+1 to REG[06h], REG[05h] of the panel contain Screen 2 ...
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... Address. The remaining 33 lines show an image from the Screen 2 Start Word Address. Hardware Functional Specification Issue Date: 02/02/01 Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) + Line 0 Line 1 Line=(REG[14h], REG[13h]) 8(REG[04h]+1) Pixels Virtual Image (8(REG[04h]+1) BPP/16)) Words ((REG[06h], REG[05])+1) Lines REG[12h] Words S1D13704 X26A-A-001-06 Page 65 ...
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... RGB Index n/a n/a The S1D13704 has three 16-position, 4-bit wide Look-Up Tables, one each for red, green, and blue. Refer to “Look-Up Table Architecture” for details. This register selects which Look-Up Table position is read/write accessible through the Look-Up Table Data Register (REG[17h]). ...
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... These two bits select which bank is used for display data. Hardware Functional Specification Issue Date: 02/02/01 Red Bank Green Bank Select Select Bit 1 Bit 0 Bit 1 Read/Write Green Bank Blue Bank Blue Bank Select Select Select Bit 0 Bit 1 Bit 0 S1D13704 X26A-A-001-06 Page 67 ...
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... When the GPIOn pin is configured as an input, the corresponding GPIO Status bit is used to read the pin input. See REG[18h] above. When the GPIOn pin is configured as an output, the corresponding GPIO Status bit is used to control the pin output. S1D13704 X26A-A-001-06 Look-Up n/a ...
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... Mode Enable Mode Select (REG[1Bh] bit 7) (REG[1Bh] bit Read/Write Scratch bit 2 Scratch bit 1 Scratch bit 0 Read/Write SwivelView SwivelView Mode Pixel Mode Pixel reserved Clock Select Clock Select Bit 1 Bit 0 Mode Landscape Default SwivelView Alternate SwivelView S1D13704 X26A-A-001-06 Page 69 ...
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... This register may be used to create a virtual image in SwivelView mode. REG[1Eh] and REG[1Fh] REG[1Eh] and REG[1Fh] are reserved for factory S1D13704 testing and should not be written. Any value written to these registers may result in damage to the S1D13704 and/or any panel connected to the S1D13704. S1D13704 X26A-A-001-06 ...
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... PCLK HDP = Horizontal Display Period = ((REG[04h] bits 6- Pixels HNDP = Horizontal Non-Display Period = ((REG[08h] bits 4- Pixels VDP = Vertical Display Period = ((REG[06h] bits 1-0, REG[05h] bits 7- Lines VNDP = Vertical Non-Display Period = (REG[0Ah] bits 5-0) Lines + VNDP + VNDP 2 X26A-A-001-06 Page 71 S1D13704 ...
Page 78
... Display Data Formats 1-bpp: Byte 0 Host Address 2-bpp: Byte 0 Byte 1 Host Address 4-bpp: Byte 0 Byte 1 Byte 2 Host Address 8-bpp: Byte 0 Byte 1 Byte 2 Host Address Figure 10-1: 1/2/4/8 Bit-Per-Pixel Display Data Memory Organization S1D13704 X26A-A-001-06 bit 7 bit ...
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... Gray Data Format See Section 10 4-bit display data output X26A-A-001-06 Page S1D13704 ...
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... Gray Shade Mode 16 Gray Data Format See Section 10 4-bit pixel data Figure 11-3: 16-Level Gray-Shade Mode Look-Up Table Architecture S1D13704 X26A-A-001-06 Green Look-Up Table Bank Bank Bank 2 3 Select ...
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... Figure 11-4: Look-Up Table Bypass Mode Architecture Note In 1 bit-per-pixel display mode, Look-Up Table Bypass mode will turn off the FRM circuitry and place the S1D13704 in Black-and-White mode bit-per-pixel mode the Display Data Output values are and F (in hex). Hardware Functional Specification ...
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... Page 76 11.2 Color Display Modes 2-Level Color Mode 1-bit pixel data Red Bank Select REG[16h] bits [5:4] Green Bank Select REG[16h] bits [3:2] Blue Bank Select REG[16h] bits [1:0] Figure 11-5: 2-Level Color Look-Up Table Architecture S1D13704 X26A-A-001-06 Red Look-Up Table Bank 3 Select Logic 4 ...
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... Blue Look-Up Table Bank Bank 4-bit ‘Blue’ display data output Bank 2 3 Select Bank 2 Logic Bank Page 77 4 Color Data Format See Section 10 S1D13704 X26A-A-001-06 ...
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... See Section 10 4-bit pixel data Figure 11-7: 16-Level Color Mode Look-Up Table Architecture S1D13704 X26A-A-001-06 Red Look-Up Table 16x4 4-bit ‘Red’ display data output Green Look-Up Table 16x4 ...
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... REG[16h] bit 2 Blue Look-Up Table 0 2-bit pixel data Blue Bank Select REG[16h] bits [1:0] Bank 0 Bank Select Bank 1 Logic Bank 0 Bank Select Bank 1 Logic Bank 0 Bank 1 Bank Select Bank 2 Logic Bank 3 Page 79 S1D13704 X26A-A-001-06 ...
Page 86
... Many of todays applications use the LCD panel in a portrait orientation. In this case it becomes necessary to “rotate” the displayed image. This rotation can be done by software at the expense of performance or, as with the S1D13704, it can be done by hardware with no CPU penalty. There are two SwivelView modes: Default SwivelView and Alternate SwivelView. ...
Page 87
... Vertical panning by a single line is not supported in Default SwivelView Mode. Hardware Functional Specification Issue Date: 02/02/01 = AddressOfPixelB = AddressOfPixelA = AddressOfPixelA = AddressOfPixelA 256 256 REG 1Ch = ----------------------------------------- - = -------- - 8bpb 4bpp 2 + ByteOffset 240pixels 4bpp -------------------------------------------- + – 1 8bpb + 77h = 128 = 80h X26A-A-001-06 Page 81 S1D13704 ...
Page 88
... Alternate SwivelView Mode is higher than in Default SwivelView Mode. The following figure shows how the programmer sees a 240x160 image and how the image is being displayed. The application image is written to the S1D13704 in the following sense: A–B–C–D. The display is refreshed by the S1D13704 in the following sense: B-D- A-C. physical ...
Page 89
... A0h to pan by one line in the example above Hardware Functional Specification Issue Date: 02/02/01 = AddressOfPixelB = AddressOfPixelA = AddressOfPixelA = AddressOfPixelA 160 160 REG 1Ch = ----------------------------------------- - = -------- - 8bpb 8bpp 1 + ByteOffset 160pixels 8bpp -------------------------------------------- + – 1 8bpb + 9Fh = 160 = A0h X26A-A-001-06 Page 83 S1D13704 ...
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... Panning Performance 12.4 SwivelView Mode Limitations The only limitation to using SwivelView mode on the S1D13705. is that split screen operation is not supported. S1D13704 X26A-A-001-06 Default SwivelView Mode The width of the rotated image must be a power most cases, a virtual image is required where the right-hand side of the virtual image is unused and memory is wasted ...
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... Epson Research and Development Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13704 to accommodate the need for power reduction in the hand-held devices market. These modes are enabled as follows: Hardware Power Save Not Configured or 0 Not Configured or 0 ...
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... Panel Power Up/Down Sequence After chip reset or when entering/exiting a power save mode, the Panel Interface signals follow a power on/off sequence shown below. This sequence is essential to prevent damage to the LCD panel. S1D13704 X26A-A-001-06 Table 13-4: Power Save Mode Function Summary Hardware Power Save ...
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... BCLK must be present for at least one T Hardware Functional Specification Issue Date: 02/02/ frame 127 frames power-up power-down Figure 13-1: Panel On/Off Sequence BCLK 00 11 Power Save Mode 0 frame power-up + 12T ] after the end of the BCLK MCLK before the start of an access. S1D13704 X26A-A-001-06 Page 87 ...
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... Page 88 13.6 Clock Requirements The following table shows what clock is required for which function in the S1D13704. Table 13-5: S1D13704 Internal Clock Requirements Function Is required during register accesses. BCLK can be shut down between accesses: allow eight BCLK pulses plus 12 MCLK pulses Register Read/Write (8T before shutting BCLK off. Allow one BCLK ...
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... Epson Research and Development Vancouver Design Center 14 Mechanical Data QFP14 - 80 pin 61 80 Hardware Functional Specification Issue Date: 02/02/01 ± 0.4 14.0 ± 0.1 12.0 60 Index 1 + 0.1 0.18 0.5 - 0.05 Figure 14-1: Mechanical Drawing QFP14 Unit 0~10° ± 0.2 0.5 1.0 X26A-A-001-06 Page 89 S1D13704 ...
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... Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/ S1D13704 X26A-A-001-06 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www ...
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... S1D13704 Embedded Memory Color LCD Controller Programming Notes and Examples Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13704 X26A-G-002-03 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/12 ...
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... LCD Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 SwivelView™ 7.1 Introduction To SwivelView . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.2 Default SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.3 Alternate SwivelView Mode . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.5 Limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.6 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8 Identifying the S1D13704 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9 Hardware Abstraction Layer (HAL 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Programming Notes and Examples Issue Date: 01/02/12 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Page 3 S1D13704 X26A-G-002-03 ...
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... Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.6 Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.2.7 LUT Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 10.1.1 Sample code using the S1D13704 HAL API . . . . . . . . . . . . . . . . . . . . . 61 10.1.2 Sample code without using the S1D13704 HAL API . . . . . . . . . . . . . . . . . 64 10.1.3 Header Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 S1D13704 X26A-G-002-03 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/12 ...
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... Epson Research and Development Vancouver Design Center Table 2-1: S1D13704 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 4-1: 2 Bpp Banking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4-2: 4 Bpp Banking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4-3: 8 Bpp Banking Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 4-4: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 4-5: Recommended LUT Values for 1 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . 20 Table 4-6: LUT Values for 2 Bpp Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 4-7: Suggested LUT Values to Simulate VGA Default 16 Color Palette ...
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... Page 6 S1D13704 X26A-G-002-03 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/12 ...
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... Epson Research and Development Vancouver Design Center 1 Introduction This guide describes how to program various features of the S1D13704 Embedded Memory Color LCD controller. The demonstrations include descriptions of how to calculate register values and explanations of how or why you might want to do certain procedures. This guide also introduces the Hardware Abstraction Layer (HAL), which is designed to simplify the programming of the S1D13704 ...
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... The notes column comments the reason for the particular value being written. This example writes to all the control registers. In practice, it may be possible to write to only a subset of the registers. When the S1D13704 is first powered up all registers, unless noted otherwise in the specification, are set to zero. This example programs these registers to zero to establish a known state. ...
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... These registers are reserved and should not be written to. 2.1 Frame Rate Calculation The system the S1D13704 is being configured for dictates certain physical constraints such as the width and height of the panel and the video system input clock. The following are the formulae for determining the frame rate of a panel. The frame rate ...
Page 106
... Unable to set the desired frame rate.\n"); exit(1); } S1D13704 X26A-G-002-03 // Solve for VNDP. VNDP = (PCLK / (FrameRate * (HDP + HNDP))) - VDP have satisfied VNDP then we're done. if ((VNDP >= 0) && (VNDP <= 0x3F)) goto DoneCalc ...
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... Vancouver Design Center 3 Memory Models The S1D13704 is capable of operating at four different color depths. The data format for each color depth is packed pixel. S1D13704 packed pixel modes can range from one byte containing eight adjacent pixels (1-bpp) to one byte containing just one pixel (8-bpp). ...
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... Look-Up Table. For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look-Up Table. Bit 7 Bit 6 Pixel 0 Pixel 0 Pixel 0 Bit 3 Bit 2 Figure 3-3: Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer S1D13704 X26A-G-002-03 Bit 5 Bit 4 Bit 3 Pixel 1 Pixel 2 Bit 1 Bit 0 Bit 1 ...
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... Red bit 1 Red bit 0 Figure 3-4: Pixel Storage for 8 Bpp (256 Colors) in One Byte of Display Buffer Programming Notes and Examples Issue Date: 01/02/12 Bit 5 Bit 4 Bit 3 Green bit 2 Green bit 1 Bit 2 Bit 1 Bit 0 Green bit 0 Blue bit 1 Blue bit 0 S1D13704 X26A-G-002-03 Page 13 ...
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... LUT registers, recommendations for the color and monochrome LUT values, and additional programming considerations for the LUT. The S1D13704 Look-Up Table consists of sixteen 4-bit wide entries for each of red, green and blue. The Look-Up Table is controlled by three registers. REG[15h] forms the index into the table ...
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... LUT addresses 4 and 5). Blue pixels would be taken from the 1st blue lookup bank (blue LUT addresses 0 and 1). Programming Notes and Examples Issue Date: 01/02/12 Red Bank Green Bank Green Bank Select bit 0 Select bit 1 Select bit 0 Page 15 Read/Write Blue Bank Blue Bank Select bit 1 Select bit0 S1D13704 X26A-G-002-03 ...
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... As with 1-bpp, the bank select bits determine the initial offset into the Look-Up Table. Incrementing a bank select by one bumps the Look-Up Table offset by four. Bank S1D13704 X26A-G-002-03 Table 4-1: 2 Bpp Banking Scheme Red LUT Green LUT Addresses Addresses 0 ...
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... Table 4-2: 4 Bpp Banking Scheme Red LUT Green LUT Addresses Addresses Addresses Blue LUT X26A-G-002-03 Page 17 S1D13704 ...
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... The 16 addresses of the Look-Up Table are divided into 2 eight-element banks for the red and green components and 4 four-element banks for the blue component. Red/Green Bank 0 1 S1D13704 X26A-G-002-03 Table 4-3: 8 Bpp Banking Scheme Red LUT Green LUT Addresses Addresses ...
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... Indicates the Look-Up Table is not used for that display mode Read/Write LUT Data LUT Data LUT Data Bit 2 Bit 1 Bit 0 Blue 4 banks banks bank banks of 4 S1D13704 X26A-G-002-03 Page 19 ...
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... Page 20 Color Modes 1 Bpp Color When the S1D13704 is configured for 1 bit-per-pixel color mode, only the first two colors from the active bank are displayed. The two entries can be set to any color but are typically set to black and white. Each byte in the display buffer contains 8 bits, each bit represents an individual pixel. A bit value of " ...
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... Vancouver Design Center 4 Bpp Color When the S1D13704 is configured for 4 bit-per-pixel operation all sixteen Look-Up Table entries are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT. ...
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... The eight red, eight green and four blue entries can be set to any color. The S1D13704 LUT has four bits (16 levels) of intensity control per primary color while a standard VGA RAMDAC has six bits (64 levels). This four to one difference has to be considered when attempting to match colors between a VGA RAMDAC and the S1D13704 LUT ...
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... Issue Date: 01/02/12 Address Red Green ... Normally unused entries Red Green ... Normally unused entries Blue Blue X26A-G-002-03 Page 23 S1D13704 ...
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... Page 24 4 Bpp Gray Shade The 4 bpp gray shade mode uses all 16 LUT elements. Table 4-11: Suggested LUT Values for 4 Bpp Gray Shade S1D13704 X26A-G-002-03 Index Red Green ...
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... The display panel is 320x240 pixels, an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling. Programming Notes and Examples Issue Date: 01/02/12 320x240 Viewport 640x480 “Virtual” Display Figure 5-1: Viewport Inside a Virtual Display Page 25 S1D13704 X26A-G-002-03 ...
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... We require a total of 640 pixels. The horizontal display register will account for 320 pixels, this leaves 320 pixels for the Memory Address Offset register to account for. offset = pixels / pixels_per_word = 320 / 28h The Memory Address Offset register, REG[12h], will have to be set to 28h to satisfy the above condition. S1D13704 X26A-G-002-03 Memory Memory Address ...
Page 123
... Both panning and scrolling are performed by modifying the start address register. Start address refers to the word offset in the display buffer where the image will start being displayed from. The start address registers in the S1D13704 are an offset to the first word to be displayed in the top left corner of every frame. ...
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... To pan to the right increase the start address value by one. To pan to the left decrease the start address value. Keep in mind that, with the exception of 8 bit-per-pixel SwivelView mode, the display will jump by more than one pixel as a result of changing the start address registers. S1D13704 X26A-G-002-03 Start Addr Start Addr ...
Page 125
... StartWord -= words_per_line; if (StartWord < 0) StartWord = 0; SetStartAddress(StartWord); To scroll down. StartWord = GetStartAddress(); StartWord += words_per_line; SetStartAddress(StartWord); long GetStartAddress (void) { return (REG[0D] * 256 +REG[0C]; } void SetStartAddress (long StartWord) { REG[0C] = StartWord & 0xFF; REG[0D] = StartWord / 256; } Programming Notes and Examples Issue Date: 01/02/12 Page 29 S1D13704 X26A-G-002-03 ...
Page 126
... The status area updates far less often than the main play area. The Split Screen feature of the S1D13704 allows a programmer to setup a display for such an application. The figure below illustrates setting a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 199 and image 2 displaying from scan line 200 to scan line 239 ...
Page 127
... While not particu- larly useful even possible to set screen 1 and screen 2 to the same address. Programming Notes and Examples Issue Date: 01/02/12 Bit 4 Bit 3 Bit 2 n/a n/a n/a Figure 5-5: Screen 1 Vertical Size Page 31 Bit 1 Bit 0 Bit 9 Bit 8 S1D13704 X26A-G-002-03 ...
Page 128
... Screen 2 requires 6400 bytes (0 to 6399) therefore the start address offset for screen 1 must be 6400 bytes. (6400 bytes = 3200 words = C80h words) Set the Screen 1 Start Word Address MSB, REG[0Dh], to 0Ch and the Screen 1 Start Word Address LSB, REG[0Ch], to 80h. S1D13704 X26A-G-002-03 Start Addr Bit Start Addr Bit ...
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... Screen 2 display data is coming from the very beginning of the display buffer. All there here is ensure that both the LSB and MSB of the Screen 2 Start Word Address registers are set to zero. Programming Notes and Examples Issue Date: 01/02/12 Page 33 S1D13704 X26A-G-002-03 ...
Page 130
... LCD. The time intervals vary depending on the power supply design. One frame after a power save mode has been enabled the S1D13704 disables LCD power. One hundred and twenty seven frames later the LCD logic signals are disabled. There may be situations where the internal time delay is insufficient to discharge the LCD power supply before the LCD signals are shut down ...
Page 131
... The following is the recommended sequence for manually powering-down an LCD panel. These steps would be used if power supply timing requirements were larger than the timings built into the S1D13704 power disable sequence. 1. Set REG[03h] bit 3, LCDPWR Override, to "1" (disables LCD Power). 2. Count "x" Vertical Non-Display Periods. ...
Page 132
... Many of todays applications use the LCD panel in a portrait orientation. In this case it becomes necessary to “rotate” the displayed image. This rotation can be done by software at the expense of performance or, as with the S1D13704, it can be done by hardware with no performance penalty. There are two hardware rotated modes: Default SwivelView Mode and Alternate SwivelView Mode ...
Page 133
... Default SwivelView Mode. The following figure shows how the programmer sees a 240x160 image and how the image is being displayed. The application image is written to the S1D13704 in the following sense: A–B–C–D. The display is refreshed by the S1D13704 in the following sense: B-D- A-C. Programming Notes and Examples ...
Page 134
... A SwivelView window C 160 image seen by programmer = image in display buffer Figure 7-2: Relationship Between The Screen Image and the Image Refreshed by S1D13704 S1D13704 X26A-G-002-03 B display start address D Epson Research and Development Vancouver Design Center 240 image refreshed by S1D13704 ...
Page 135
... Mode Select The SwivelView mode register contains several items for SwivelView mode support. The first is the SwivelView Mode Enable bit. When this bit is “0” the S1D13704 is in landscape mode and the remainder of the settings in this register as well as the Line Byte Count in REG[1Ch] are ignored. When this bit is a “ ...
Page 136
... SwivelView mode due to a lack of memory may now be used. Clocking for the S1D13704 works as follows: An external clock source supplies CLKI, the input clock. CLKI is routed through the Input Clock Divide from Mode Register 1 (REG[02h] bit 4) and is either divided by two or passed on ...
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... Epson Research and Development Vancouver Design Center 7.5 Limitations The only limitation to using SwivelView mode on the S1D13704 is that split screen operation is not supported. A comparison of the two SwivelView modes is as follows: Table 7-1: Default and Alternate SwivelView Mode Comparison Item The width of the rotated image must be a power of 2 ...
Page 138
... The only thing to keep in mind is that the count from the first pixel of one line to the first pixel of the next line (refered to as the "stride") is 128 bytes. S1D13704 X26A-G-002-03 Epson Research and Development ...
Page 139
... Note These examples don’t use the Pixel Clock Select bits. The ability to divide the PCLK value down further than the default values was added to the S1D13704 to support SwivelView mode on very small panels. The Pixel Clock value has changed so we must calculate horizontal and vertical non-display times to reach the desired frame rate ...
Page 140
... Display memory is accessed exactly as it was for landscape mode. As this is the alternate SwivelView mode the power of two stride issue encountered with the default SwivelView mode is no longer an issue. The stride is the same as the SwivelView mode width. In this case 120 bytes. S1D13704 X26A-G-002-03 PCLK FrameRate = ...
Page 141
... In this case 281h (81h + 200h) will be written to the Screen 1 Start Word Address reg- ister pair. Set Screen1 Display Start Word Address LSB (REG[0Ch]) to 81h and Screen1 Display Start Word Address MSB (REG[0Dh]) to 02h. Programming Notes and Examples Issue Date: 01/02/12 scroll pixels. Page 45 S1D13704 X26A-G-002-03 ...
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... It may be important for a program to identify between products at run time. Identification of the S1D13704 can be performed any time after the system has been powered up by reading REG[00h], the Revision Code register. The six most significant bits form the product identification code and the two least significant bits form the product revision ...
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... Programming Notes and Examples Issue Date: 01/02/12 Registers the S1D13704 device parameters with the HAL library. The device param- eters have been configured with address range, register values, desired frame rate, etc., and have been saved in the HAL_STRUCT structure pointed to by lpHalInfo. ...
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... X26A-G-002-03 Configures the S1D13704 for operation. This function sets all the S1D13704 control registers to their default values. Initialization of the S1D13704 was made a stand-alone step to accommodate those programs (e.g. 13704PLAY.EXE) which needed the ability to start and examine the system before changing register contents. ...
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... Description: Parameters: Return Value: None Programming Notes and Examples Issue Date: 01/02/12 Reads the S1D13704 revision code register to determine the chip product and revisions. The interpreted value is returned in pID. DevID - registered device ID pId - pointer to an integer which will receive the controller ID. ...
Page 146
... S1D13704. This function reads the S1D13704 registers to determine the current color depth and returns the result in pBitsPerPixel. DevID - registered device ID pBitsPerPixel - pointer to an integer to receive current color depth ...
Page 147
... The S1D13704 registers must be initialized for this function to work correctly. On the PC platform this is simply a call to the C timing functions and is therefore independent of the register settings. ...
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... S1D13704 X26A-G-002-03 - operation completed with no problems This function call enables or disable the high performance bit of the S1D13704. When high performance is enabled then MClk equals PClk for all video display resolutions. In the high performance state CPU to video memory performance is improved at the cost of higher power consumption. ...
Page 149
... The smallest surface screen 1 can display is one line. This is due to the way the S1D13704 operates. Setting Screen 1 Vertical Size to zero results in one line of screen 1 being displayed. The remainder of the display will be screen 2 image. DevID ...
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... Return Value: ERR_OK - operation completed with no problems Note seVirtInit() must be been called before calling seVirtMove(). S1D13704 X26A-G-002-03 This function prepares the system for virtual screen operation. The programmer passes the desired virtual width, in pixels, as VirtX. When the routine returns VirtY will contain the maximum number of line that can be displayed at the requested virtual width ...
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... Epson Research and Development Vancouver Design Center 9.2.4 Register / Memory Access The Register/Memory Access functions provide access to the S1D13704 registers and display buffer through the HAL. int seGetReg(int DevID, int Index, BYTE * pValue) Description: Parameters: Return Value: ERR_OK int seSetReg(int DevID, int Index, BYTE Value) ...
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... Return Value: ERR_OK - operation completed with no problems. int seWriteDisplayBytes(int DevID, DWORD Offset, BYTE Value, DWORD Count) Description: Parameters: Return Value: ERR_OK S1D13704 X26A-G-002-03 Reads a word from the display buffer at the specified offset and returns the value in pWord. DevID - registered device ID ...
Page 153
... If a count greater than one is specified all DWORDSs will have the same value. DevID - registered device ID Offset - offset from start of the display buffer Value - DWORD value to write Count - number of dwords to write - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Addr or if Addr plus Count is greater than 40 kb. Page 57 S1D13704 X26A-G-002-03 ...
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... Description: Parameters: Return Value: ERR_OK - operation completed with no problems S1D13704 X26A-G-002-03 This function sets on the S1D13704’s software selectable power save modes. DevID - a registered device ID PwrSaveMode - integer value specifying the desired power save mode. Acceptable values for PwrSaveMode are (software power save mode) in this mode registers and memory are read/writable ...
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... A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue. The color information is stored in the four least significant bits of each byte. DevID - registered device ID pLut - pointer to an array of BYTE lut[16][3] lut[x][0] == RED component lut[x][1] == GREEN component lut[x][2] == BLUE component Count - the number of LUT entries to write. Page 59 S1D13704 X26A-G-002-03 ...
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... DevID, int index, BYTE *pEntry) Description: Parameters: Return Value: ERR_OK - operation completed with no problems S1D13704 X26A-G-002-03 This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT. A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue. ...
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... Sample Code 10.1 Introduction Included in the sample code section are two examples of programing the S1D13704. The first sample uses the HAL to draw a red square, wait for user input then rotates to SwivelView mode and draws a blue square. The second sample code performs the same procedures but directly accesses the registers of the S1D13704 ...
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... Page 62 { printf("\nERROR: Could not register S1D13704 device."); exit(1 Get the product code to verify this is an S1D13704. ** NOTE: If the S1D13704 design is modified then the ** product identification change. Additional IDs ** will have to be checked for. */ seGetId(Device, &ChipId); if (ID_S1D13704F00A != ChipId) { printf("\nERROR: Did not detect an S1D13704."); ...
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... Epson Research and Development Vancouver Design Center seSetHWRotate(Device, PORTRAIT Draw a solid blue 100x100 rectangle in center of the display. ** This starting co-ordinates, assuming a 320x240 display is ** (320-100)/2 , (240-100)/2 = 110,70. */ seDrawRect(Device, 110, 70, 210, 170, 2, TRUE Done! */ exit(0); } Programming Notes and Examples Issue Date: 01/02/12 Page 63 S1D13704 X26A-G-002-03 ...
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... This second sample demonstrates exactly the same sequence as the first howerver the HAL is not used, all manipulation is done by manually adjusting the registers. /* **=========================================================================== ** SAMPLE2.C - Sample code demonstating a direct access of the S1D13704. **------------------------------------------------------------------------- ** Created 1998, Vancouver Design Centre ** Copyright (c) 1998 Epson Research and Development, Inc. ...
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... Location is platform dependent */ /* 40 kb display buffer. /* Some usefule typedefs */ ((BYTE)(w)) ((BYTE)(((WORD)(w) >> 8) & 0xFF)) (*(LPBYTE)(REG_OFFSET + idx)) = (val) Page S1D13704 X26A-G-002-03 ...
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... Page Check the revision code. Exit if we don't find an S1D13704 (0x18 != *pRegs) return Initialize the chip. ** Each register is individually programmed to make comments clearer Register 01h: Mode Register 0 - Color, 8-bit format 2 */ SET_REG(0x01, 0x23 Register 02h: Mode Register 1 - 4BPP, */ SET_REG(0x02, 0xB0 Register 03h: Mode Register 2 - Normal power mode */ SET_REG(0x03, 0x03) ...
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... Register 13h - Screen 1 Vertical Size LSB ** Register 14h - Screen 1 Vertical Size MSB Programming Notes and Examples Issue Date: 01/02/12 (HDP + HNDP) * (VDP + VNDP) achieve the desired frame rate. display size. Usually set to 0 during initialization and programmed to desired value later. Page 67 S1D13704 X26A-G-002-03 ...
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... SET_REG(0x18, 0x00 Register 19h - GPIO Status - set This step has no reason other than it programs the GPIO S1D13704 X26A-G-002-03 for split screen operation and should be set to 0 during initialization. appearance at other color depths. Epson Research and Development Vancouver Design Center ...
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... Pause here. */ getch(); /* ** Clear the display, and all of video memory, by writing 40960 bytes of 0. Programming Notes and Examples Issue Date: 01/02/12 values low should the pins get configured as outputs. /* Draws 2 pixels with LUT color 4 */ Page 69 S1D13704 X26A-G-002-03 ...
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... MCLK will be <= 25 MHz so we can leave auto-switch enabled. */ SET_REG(0x1B, 0x80 Draw a solid blue 100x100 rectangle centered on the display. ** Starting co-ordinates, assuming a 320x240 display are: ** (320-100)/2 , (240-100)/2 = 110,70. */ for (y = 70; y < 180; y++) { /* S1D13704 X26A-G-002-03 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/12 ...
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... NOTICE that in SwivelView mode we will use a value of 256 ** for the line width value (not 240 110; pMem = (LPBYTE)MEM_OFFSET + (y * 256 * BitsPerPixel / 8) + for (x = 110; x < 210; x+=2) { *pMem = 0x11; pMem++; } } } Programming Notes and Examples Issue Date: 01/02/ BitsPerPixel / 8); /* Draws 2 pixels in LUT color 1 */ Page 71 S1D13704 X26A-G-002-03 ...
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... The header files included here are the required for the HAL sample to compile correctly. /* **=========================================================================== ** HAL.H - Typical HAL header file for use with programs written to ** use the S1D13704 HAL. **--------------------------------------------------------------------------- ** Created 1998, Vancouver Design Centre ** Copyright (c) 1998 Epson Research and Development, Inc. ** All Rights Reserved. ...
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... DPF1(exp) printf(#exp " = %d\n", exp) #define DPF2(exp1, exp2) printf(#exp1 "=%d #define DPFL(exp) printf(#exp " = %x\n", exp) #else #define DPF(exp) ((void)0) #define DPF1(exp) ((void)0) #define DPFL(exp) ((void)0) #endif Programming Notes and Examples Issue Date: 01/02/12 " #exp2 "=%d\n", exp1, exp2) Page 73 S1D13704 X26A-G-002-03 ...
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... MIN_NON_DISP_X #define MAX_NON_DISP_X #define MIN_NON_DISP_Y #define MAX_NON_DISP_Y /******************************************* * Definitions for seSetFont *******************************************/ enum { HAL_STDOUT, HAL_STDIN, HAL_DEVICE_ERR }; #define FONT_NORMAL S1D13704 X26A-G-002- error, call was successful General purpose failure Function was called with invalid parameter. */ 40960 0 32 256 2 64 0x00 Epson Research and Development ...
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... BOOL OnOff ); /*------------------------------- Advanced --------------------------------*/ int seSetHWRotate( int nDevID, int nMode ); Programming Notes and Examples Issue Date: 01/02/12 0x01 0x02 /* Input Clock Frequency (in kHz FUNCTION PROTO-TYPES Page 75 */ S1D13704 X26A-G-002-03 ...
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... BYTE *pEntry ); int seGetLutEntry( int nDevID, int index, BYTE *pEntry ); #endif /* _HAL_H_ */ /*--------------------------------------------------------------------------*/ /* **=========================================================================== ** APPCFG.H - Application configuration information. **--------------------------------------------------------------------------- ** Created 1998, Vancouver Design Centre S1D13704 X26A-G-002-03 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/12 ...
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... Programming Notes and Examples Issue Date: 01/02/ 0x27, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* ClkI (kHz) /* Display Address */ ** Panel Frame Rate (Hz) */ All rights reserved. Page S1D13704 X26A-G-002-03 ...
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... REG_SCRATCHPAD #define REG_PORTRAIT_MODE #define REG_LINE_BYTE_COUNT #define REG_NOT_PRESENT_1 #define REG_FRAMING #define REG_TEST_MODE /* ** WARNING!!! MAX_REG must be the last available register!!! */ #define MAX_REG #endif /* __HAL_REGS_H__ */ S1D13704 X26A-G-002-03 Epson Research and Development Vancouver Design Center 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 ...
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... Epson Research and Development Vancouver Design Center Appendix A Supported Panel Values A.1 Introduction Future versions of this document will supply example tables for programming the S1D13704 for different panels. Programming Notes and Examples Issue Date: 01/02/12 Page 79 S1D13704 X26A-G-002-03 ...
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... Page 80 S1D13704 X26A-G-002-03 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/12 ...
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... S1D13704 Embedded Memory Color LCD Controller 13704CFG Configuration Program Document Number: X26A-B-001-03 Copyright © 1998, 2002 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products ...
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... Page 2 S1D13704 X26A-B-001-03 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13704CFG Configuration Program Issue Date: 02/03/11 ...
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... General Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Preferences Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Clocks Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Panel Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Panel Power Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Registers Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 13704CFG Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Open... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Save As... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Configure Multiple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Export . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Enable Tooltips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ERD on the Web . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 About 13704CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13704CFG Configuration Program Issue Date: 02/03/11 Table of Contents Page 3 S1D13704 X26A-B-001-03 ...
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... Page 4 S1D13704 X26A-B-001-03 THIS PAGE LEFT BLANK Epson Research and Development Vancouver Design Center 13704CFG Configuration Program Issue Date: 02/03/11 ...
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... Windows® program that calculates register values for a user- defined S1D13704 configuration. The configuration information can be used to directly alter the operating characteristics of the S1D13704 utilities or any program built with the Hardware Abstraction Layer (HAL) library. Alternatively, the configuration information can be saved in a variety of text file formats for use in other applications ...
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... Page 6 Installation Create a directory for 13704cfg.exe and the S1D13704 utilities. Copy the files 13704cfg.exe and panels.def to that directory. Panels.def contains configuration infor- mation for a number of panels and must reside in the same directory as 13704cfg.exe. Usage To start 13704CFG from the Windows desktop, double-click on the My Computer icon and run the program 13704cfg ...
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... Configuration Tabs 13704CFG provides a series of tabs which can be selected at the top of the main window. Each tab allows the configuration of a specific aspect of S1D13704 operation. The tabs are labeled “General”, “Preference”, “Clocks”, “Panel”, “Panel Power”, and “ ...
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... PCI interface and the decode addresses are determined by the system BIOS during boot-up. If using the S1D13704 Evaluation Board on a PCI based platform, both Windows and the S1D13XXX device driver must be installed. For further information on the S1D13XXX device driver, see the S1D13XXX 32-bit Windows Device Driver Installa- tion Guide, document number X00A-E-003-xx ...
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... Configuration Program Issue Date: 02/03/11 Sets the initial color depth on the LCD panel. The S1D13704 SwivelView feature is capable of rotating the image displayed on an LCD panel 90° counter-clockwise direction. This sets the initial orien- tation of the panel. The SwivelView feature can be run in two different modes ...
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... CLKI The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals. For further information regarding clocking and clock sources, refer to the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx. Note Options for LCD frame rates are limited to ranges determined by the clock values. Also, changing clock values may modify or invalidate Panel settings ...
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... Epson Research and Development Vancouver Design Center The S1D13704 uses one clock input known as CLKI. The pixel clock (PCLK) and the memory clock (MCLK) are both derived directly from CLKI. CLKI CLKI/2 PCLK Source Divide Timing MCLK Source Divide Timing 13704CFG Configuration Program Issue Date: 02/03/11 This setting establishes the frequency of CLKI ...
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... Panel Data Width Format 2 Panel Type Frame Repeat Non-display Periods Panel Dimensions TFT/FPLINE The S1D13704 supports many panel types. This tab allows configuration of most panel settings such as panel dimensions, type and timings. Panel Type S1D13704 X26A-B-001-03 Panel Color FPLINE Dual Panel ...
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... Issue Date: 02/03/11 Selects color STN panel format 2. This option is specif- ically for configuring 8-bit color STN panels. See the S1D13704 Hardware Functional Specification, document number X26A-A-001-xx, for description of format 1 / format 2 data formats. Most new panels use the format 2 data format. ...
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... Specifies the delay (in pixels) from the start of the horizontal non-display period to the leading edge of the FPLINE pulse. This setting is only available when the selected panel type is TFT. Refer to S1D13704 Hardware Functional Specifi- cation, document number X26A-A-001-xx for a complete description of the FPLINE pulse settings. 13704CFG Configuration Program ...
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... FPFRAME pulse. This settings is only available when the selected panel type is TFT. Refer to S1D13704 Hardware Functional Specifi- cation, document number X26A-A-001-xx, for a complete description of the FPFRAME pulse settings. 13704CFG uses a file (panels.def) which lists various panel manufacturers recommended settings ...
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... GPIO0 is enabled. When this box is unchecked, the Hardware Power Save function is not available. This setting controls the time delay between when the LCD panel is powered-off and when the S1D13704 control signals are turned off. This setting must be configured according to the specification for the panel being used ...
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... Vancouver Design Center Power Up Time Delay Registers Tab The Registers tab allows viewing and direct editing the S1D13704 register values. Scroll up and down the list of registers and view their configured values based on the settings in the previous tabs. Individual register settings may be changed by double- clicking on the register in the listing ...
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... This may be used to quickly arrive at a starting point for register configuration. The only requirement is that the file being opened must contain a valid S1D13704 HAL library information block. 13704CFG supports a variety of executable file formats. Select the file type(s) 13704CFG should display in the Files of Type drop-down list and then select the filename from the list and click on the Open button ...
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... BMP60Hz.EXE, BMP72Hz.EXE, BMP75Hz.EXE where only the frame rate changes in each of these files). Note When “Save As” is selected then an exact duplicate of the file as opened by the “Open” option is created containing the new configuration information. 13704CFG Configuration Program Issue Date: 02/03/11 Page 19 S1D13704 X26A-B-001-03 ...
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... MPC and IDP based programs at the same time for a new panel type, the physical addresses for each are retained. This feature is primarily intended for the test lab where multiple hardware configurations exist and are being tested. S1D13704 X26A-B-001-03 Epson Research and Development ...
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... Notepad with a copy of the configuration file about to be saved. When the C Header File for S1D13704 WinCE Drivers option is selected as the export type, additional options are available and can be selected by clicking on the Options button. The options dialog appears as: ...
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... Comments • On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13704 (i.e. Selecting TFT or STN on the Panel tab enables/disables options specific to the panel type). • The file panels.def is a text file containing operational specifications for several supported, and tested, panels. This file can be edited with any text editor. • ...