GS1540-CQR Gennum Corporation, GS1540-CQR Datasheet
GS1540-CQR
Related parts for GS1540-CQR
GS1540-CQR Summary of contents
Page 1
... The GS1540 uses the GO1515 external VCO connected to the internal PLL circuitry to achieve ultra low noise PLL performance. ORDERING INFORMATION ORDERING INFORMATION ORDERING INFORMATION ORDERING INFORMATION PART NUMBER GS1540-CQR DDOint RECLOCKER S/P CONVERTER CORE DDOint BUFFER DDO_EN SIMPLIFIED BLOCK DIAGRAM SIMPLIFIED BLOCK DIAGRAM ...
Page 2
... PARAMETER Supply Voltage ( Input Voltage Range (any input) Operating Temperature Range Storage Temperature Range Power Dissipation (V = 5.25V) CC Lead Temperature (soldering 10 seconds) Input ESD Voltage Junction Temperature GENNUM CORPORATION LBCONT LFA LFS LFS PLCAP PLCAP IJI CHARGE PHASE PUMP LOCK PHASE ...
Page 3
... Production test at room temperature and nominal supply voltage sample test. 5. Calculated result based on Level 1, Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. GENNUM CORPORATION CONDITIONS SYMBOL MIN V 4. ...
Page 4
... Digital Data Output (DDO) – Rise and Fall Time Mismatch Digital Data Output (DDO) – (RMS Jitter for clean PRN 2 Intrinsic Jitter – 1 input on DDI/DDI inputs) Loop bandwidth @ 0.2UI jitter modulation LBCONT floating Jitter peaking GENNUM CORPORATION CONDITIONS SYMBOL BR 1.485/1.001 SDI J TOL T ALOCK ...
Page 5
... Production test at room temperature and nominal supply voltage sample test. 5. Calculated result based on Level 1, Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. GENNUM CORPORATION SYMBOL MIN SMPTE 292M P 74.25/1.001 CLK_OUT ...
Page 6
... VCO VCO PLCAP PLCAP PLL_LOCK 100 101 NC NC 102 GENNUM CORPORATION GS1540 TOP VIEW PCLK_V EE 35 PCLK_V CC 34 PCLK_OUT 33 SP_V EE 32 SP_V EE 31 SP_V CC 30 SP_V ...
Page 7
... Note that these outputs are not cable drivers. Ensure that the trace length between the GS1540 and the GS1508 Cable driver is kept to a minimum and that a PCB trace characteristic impedance of 50 Ω is maintained between the GS1508 and the GS1540. 50 Ω ...
Page 8
... DDI, DDI 110 PD_V CC 112 PDSUB_V EE 113 PD_V EE GENNUM CORPORATION LEVEL TYPE Power Input Positive Supply . Loop filter most positive power supply connection. Analog Output Control Signal Output. Control voltage for GO1515 VCO. Analog Input Control Signal Input . Used to provide electronic control of Loop Bandwidth ...
Page 9
... PD_V EE DDI 50 DDI_V TT Fig. 1 DDI/DDI Input Circuit 5k 10k PD_V EE 50 VCO Fig. 2 VCO/VCO Input Circuit 10k 10k DM 85µA DFT_V Fig. 3 DM/DM Output Circuit GENNUM CORPORATION PD_V CC 50 DDI PD_V CC 5k 10k 40 31p VCO PD_V PD_V CC 20k 10k PLCAP PLCAP 100µ ...
Page 10
... LFS 100µA 100µA 100µA Fig. 7 LFS Input Circuit PD_V CC 10k PLL_LOCK PD_V Fig. 8 PLL_LOCK Output Circuit 10k 30k A PD_V EE Fig. 9 IJI Output Circuit GENNUM CORPORATION LFA_V CC 100µA BYPASS LFA_V EE EE PD_V CC IJI 10 PD_V CC 16k + V = 2.4V - 100µA ...
Page 11
... VCO), the loop corrects for that immediately thus the small signal noise of the VCO is cancelled. The GS1540 uses a very clean, external VCO called the GO1515 (refer to the GO1515 Data Sheet for details). In addition, the bi-level ...
Page 12
... Equalizer. PHASE DETECTOR The phase detector portion of the slew PLL used in the GS1540 is a bi-level digital phase detector. It indicates whether the data transition occurred before or after with respect to the falling edge of the internal clock. When the phase detector is locked, the data transition edges are aligned to the falling edge of the clock ...
Page 13
... Because the threshold is lower than 1, it allows jitter to be greater than 0.5UI before the phase lock circuit reads it as “not phase locked”. GENNUM CORPORATION INPUT JITTER INDICATOR (IJI) This signal indicates the amount of excessive jitter (beyond the quadrature clock window 0.5UI), which occurs beyond the quadrature clock window (see Figure 18) ...
Page 14
... DM/DM signal. Figure 20 shows an example of such a situation. An HDTV SDI signal is modulated with a modulation signal causing about 0.2UI jitter in Figure 20 (Channel 1). The GS1540 receives this signal and locks to it. Figure 20 (Channel 2) shows the DM signal. Notice the wave shape of the DM signal, which is synchronous to the modulating signal. The DM/DM signal could also be used to compare the output jitter of the HDTV signal source ...
Page 15
... VCO VCO PLCAP PLCAP PLL_LOCK 100 nc 101 nc 102 GENNUM CORPORATION TYPICAL APPLICATION CIRCUIT TYPICAL APPLICATION CIRCUIT TYPICAL APPLICATION CIRCUIT TYPICAL APPLICATION CIRCUIT PCLK_V 36 CC PCLK_V 35 PCLK_OUT 34 EE SP_V ...
Page 16
... APPLICATION INFORMATION APPLICATION INFORMATION Please refer to the EBHDRX documentation for more detailed application and circuit information on using the GS1540 with the GS1500 and GS1510 Deformatters. CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION PRELIMINARY DATA SHEET The product preproduction phase and specifications are subject to change without notice ...
Page 17
... PACKAGE DIMENSIONS PACKAGE DIMENSIONS PACKAGE DIMENSIONS PACKAGE DIMENSIONS 23.20 ±0.25 20.0 ±0.10 18.50 REF 0.50 BSC 0.27 ±0.08 GENNUM CORPORATION 12 TYP 17.20 ±0.25 12.50 REF 14.0 ±0.10 0.13 MIN. RADIUS 3.00 MAX 128 pin MQFP 2.80 ±0.25 All dimensions are in millimetres. 17 0.75 MIN 0.30 MAX RADIUS 0.88 ±0.15 1.6 REF 522 - ...