CMX649 CML Microcircuits, CMX649 Datasheet - Page 42

• Manufacturer Part Number: CMX649
• Description: ADM Codec
• Manufacturer: CML Microcircuits

ADM Codec
CMX649
6.3.1 32kbps ADM with clock and data recovery
//Initialize device with general reset
// This powers down everything excluding the xtal oscillator circuit
$01
//Setup analog section
// $61 00 filters set for 2.9kHz BW (default after reset)
// volume=0dB side_tone=-21dB and off
$62 $BE
// audio_level=0dB
$63 $80
// power_control everything on (lowest current setting)
$64 $55
$65 $55
// codec mode
// default $70 $00 ADM unbuffered (continuous bit serial mode)
// Clock Divider Control
// using 4.096MHz master clock
// filter clock prescale/=2 main divider/=8 => 256kHz SCF clock
// bit clock prescale/=2 encode and decode bit dividers/=1 since constant divider/=64 => 32kbps
$72 $E9 $40
// PLL is off, Bypass PLL Data Filter and Power it Down
// Internal Decode and Encode clocks from
// Decode internal clock
$73 $00 $78
// setup decoder
// decimate by 8
// decode adm input from RX Data
// adm estimator drives output
// vad attack tc=4ms and decay tc=128ms
// normal vad outputs
$D0 $00 $B8
// adm encode feedback from comparator, nulling for improved idle – otherwise as decoder
$E0 $01 $B8
// to enable offset nulling load small positive constant into encoder offset input reg
$E3 $00 $04
// adm mode syllabic tc=16ms
// step size dynamic range 5120/10
// companding rule = 4 of 4
// principal tc=0.33ms
// second order tc=0.083ms
// encoder zero tc=0.047ms decoder zero tc=N/A
// decoder zero at 16kHz i.e. bit_rate/2 enabled
$D1 $6D $51
$E1 $6D $52
// vad thresholds ~20mv
$D2 $02 $00
$E2 $02 $00
// prime idle pattern into CBUS ADM source byte regs
$D8 $AA
$E8 $AA
//Scrambler and Descrambler both on, using polynomial $14 (5 bit LFSR)
$71 $90 $14
// enable encoder and decoder with no IRQs
$81 $88
// note some useful register changes from the above settings
// force encoder to output an idle pattern ($E0 $81 $B9) (requires $E8 $AA above)
// force decoder to idle via idling its input ($D0 $88 $B8) (requires $D8 $AA above)
// force decoder to mute output via direct PCM out ($D0 $86 $B8) (reset default has $D7 $00 $00)
// turn Scrambler and Descrambler off ($71 $00 $00)
// To Make PLL run with input from data pad
// internal RX and TX clocks
// RX data input acting as analog input i.e. data filter and data slicer running
// ($73 $00 $D2)
2003 CML Microsystems Plc
42
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