MB86605 Fujitsu Microelectronics, Inc., MB86605 Datasheet - Page 23

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MB86605

Manufacturer Part Number
MB86605
Description
CMOS-wide Scsi-ii Protocol Controller With Pci Interface
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
(2) Register read timing for 80 series
Address (A4 to A0), BHE set up time
Address (A4 to A0), hold time
CS0 set up time
CS0 hold time
RD set Low
RD set high
RD pulse duration at Low
INT signal clear time
A4 to A0
BHE
CS0
RD
D15 to 8, UDP
D7 to 0, LDP
INT
INT
data output defined time
data output disable time
*: t
DL2
Parameter
is defined by the rising edge of strobe signal that reads out the step code for the last interrupt source.
Interrupt non-hold mode
Interrupt hold mode
t
ARS
t
CRS
t
DL
t
RLD
Symbol
t
t
t
t
t
t
t
t
t
ARS
ARH
CRS
CRH
RLD
RHD
RD
DL
DL2
t
RD
Min.
Valid data
40
20
20
10
70
5
t
t
Value
CRH
DL2
t
RHD
*
t
ARH
n
(n is the division ratio)
Max.
t
CLF
70
50
MB86605
+ 50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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