MB86605 Fujitsu Microelectronics, Inc., MB86605 Datasheet - Page 2

• Manufacturer Part Number: MB86605
• Description: CMOS-wide Scsi-ii Protocol Controller With Pci Interface
• Manufacturer: Fujitsu Microelectronics, Inc.

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MB86605
SCSI Protocol Controller Block:
• Operable as initiator and target
• WIDE and FAST data transfer
• 64-byte FIFO register for data phase
• Two types (send-only and receive-only) of 32-byte data buffers for message, command, and status phases
• On-chip totem pole type SCSI single-ended driver/receiver
• Supports external SCSI differential driver/receiver
• On-chip memory to store transfer parameters for each ID (up to 15 connected devices)
• On-chip 16-bit transfer block counter and 24-bit transfer byte counter
• Supports various control commands:
• On-chip direct control register for SCAM (SCSI Configured AutoMatically)
• Supports Multi Selection/Reselection Responses
• On-chip 2 Kbyte User Program Memory
• User Selectable Interrupt Report
• Two automatic receive modes
• Automatic selection/reselection
• Operation Clock
FEATURES
– Synchronous transfer (max. 20 Mbytes/s: Up to 32 offset values can be set.)
– Asynchronous transfer (max. 10 Mbytes/s)
(MCS Buffers)
– Maximum Transfer Byte
– Sequential Commands
– Discrete Commands
– Data Transfer Commands : can program the transfer data length at the user program operation.
– Selection and Reselection responses can be done to plural IDs.
– Two Modes: 2 Kbyte
– Access to User program
– Unnecessary interrupt reports can be disabled depending on user's applications to reduce a system ISR
– Initiator : can automatically receive information for new phase to which target switched
– Target : can automatically receive attention condition generated by initiator
– For command issues
– For user program operation: pauses the program currently executed and automatically jumps to the
– System Clock: Max. 40 MHz
– Internal Processor Operating Clock: Max. 20 MHz
overhead.
(While 1 Kbyte 2 banks are selected, host system can access another bank even if the user
program is executing.)
1 bank and 1 Kbyte
: 1 Tbyte at fixed length data transfer
: 6 Mbyte at variable length data transfer
: can perform phase-to-phase sequential operations (functions only when
: can perform any desired sequence to program in the user program memory
: Burst transfer via I/O access port
: Direct access to 2 Kbyte user program memory (only for PCI bus I/F mode)
: automatically performs to receive MSG/CMD to the selection/reselection
issuing from a system side.)
request from partner device
specified selection/reselection routine in response to the selection/reselection
request from partner device.
2 banks
(Continued)