MB86605 Fujitsu Microelectronics, Inc., MB86605 Datasheet - Page 15

• Manufacturer Part Number: MB86605
• Description: CMOS-wide Scsi-ii Protocol Controller With Pci Interface
• Manufacturer: Fujitsu Microelectronics, Inc.

1. Internal Processor
This processor provides the sequence control between each phase.
2. Timer
This timer manages the time specified by SCSI and the following time:
3. Phase Controller
This controller controls the arbitration, selection/reselection, data-in/out, command, status, and message-in/out
phases executed on the SCSI bus.
4. Transfer Controller
This controller controls the information (data, command, status, message) transfer phases executed on the SCSI
bus.
There are two types of transfer for executing the information transfer phases.
Depending on the data migration, there are the following two modes.
At synchronous transfer, the transfer parameters (transfer mode, minimum cycle period of REQ or ACK signal sent
from SPC in synchronous transfer, and maximum value between REQ and ACK signals in synchronous transfer)
can be saved for each ID and are automatically set when the data phase is started. The transfer byte count is
determined by block length
5. Various Registers
• REQ/ACK assertion time for data at asynchronous transfer
• Selection/reselection retry time
• Selection/reselection timeout time
• REQ/ACK timeout time during transfer
• Asynchronous transfer: Control by interlocking REQ and ACK signals
• Synchronous transfer: Control with maximum of 32-byte offset value in data-in/out phase
• Program transfer: Performed via MPU interface using data registers
• DMA transfer:
• Command register
• Nexus status register
• SCSI control signal status register
• Interrupt status register
BLOCK FUNCTIONS
This register specifies each command with an 8-bit code.
When using the user program, specify “1” at the Bit 7. The lower 7 bits (Bit6 to Bit0) are invalid.
This register indicates the chip’s operating condition, the nexused partner's ID, and data register status.
This register indicates the status of SCSI control signals.
This register indicates the interrupt status with an 8-bit code.
Asynchronous transfer (target)
Asynchronous transfer (initiator)
Synchronous transfer (target only) : Time required for target to receive ACK signal for setting offset value to
Performed via DMA interface using DREQ and DACK pins
number of blocks.
: Time required for initiator to assert ACK signal after asserting REQ
: Time required for target to negate REQ signal after asserting ACK signal
signal
0 from initiator after sending REQ signal
MB86605
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