S1D13742 Epson, S1D13742 Datasheet - Page 70

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Page 70
9.3.9 Miscellaneous Registers
bit 7
bit 1
bit 0
bit 7
S1D13742
X63A-A-001-06
REG[56h] Power Save Register
Default = 00h
REG[58h] Non-Display Period Control / Status Register
Default = 00h
PWRSVE Input
Display Period
Pin Function
Vertical Non-
Status (RO)
7
7
Horizontal Non-
Display Period
Status (RO)
6
6
Note
Note
PWRSVE Input Pin Function
When this bit = 0, the PWRSVE pin is OR’d with bit 1 (setting either to 1 will enable
Sleep Mode)
When this bit = 1, the PWRSVE pin is OR’d with bit 0 (setting either to 1 will enable
Standby Mode)
Sleep Mode Enable/Disable
When this bit = 0, Sleep Mode is disabled (normal operation)
When this bit = 1, Sleep Mode is enabled.
Sleep Mode disables all internal blocks including the PLL. When Sleep Mode is disabled
(low), the PLL requires approximately 10msec lock time before any memory access
should be attempted. The PLL Lock bit, REG[04] bit 7, can be read to verify when the
PLL becomes stable.
Standby Mode Enable/Disable
When this bit = 0, Standby Mode is disabled (normal operation)
When this bit = 1, Standby Mode is enabled
Standby Mode disables all internal blocks except the PLL. Using this mode, the chip can
be accessed immediately when Standby is disabled.
Vertical Non-Display Period Status
This is a read-only status bit.
When this bit = 0, the LCD panel output is in a Vertical Non-Display Period.
When this bit = 1, the LCD panel output is in a Vertical Display Period.
Standby Mode can also be enabled/disabled using the PWRSVE input pin.
VNDP is defined as time between the last pixel on the last line of one frame to the first
pixel on the first line of the next frame.
VS OR’d with HS
Status
(RO)
5
5
Revision 6.01 - EPSON CONFIDENTIAL
YYC Last Line
n/a
4
4
w
3
n/a
w
3
w
.
D
a
TE Output Pin
t
Enable
2
a
2
S
h
e
Epson Research and Development
e
Enable/Disable
TE Output Pin Function Select bits 1-0
Hardware Functional Specification
Sleep Mode
t
.
1
c
1
Vancouver Design Center
o
Issue Date: 2007/09/18
.
k
r
Read/Write
Read/Write
Enable/Disable
Standby Mode
0
0
D
a
t
a