S1D13742 Epson, S1D13742 Datasheet - Page 39

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

Epson Research and Development
Vancouver Design Center
1. Ts
Hardware Functional Specification
Issue Date: 2007/09/18
Symbol
t10
t11
t12
t13
t14
t15
t16
t17
t18
t1
t2
t3
t4
t5
t6
t7
t8
t9
= pixel clock period
VS cycle time
VS pulse width low
VS falling edge to HS falling edge phase difference
HS cycle time
HS pulse width low
HS Falling edge to DE active
DE pulse width
DE falling edge to HS falling edge
PCLK period
PCLK pulse width low
PCLK pulse width high
HS setup to PCLK active edge
DE to PCLK rising edge setup time
DE hold from PCLK active edge
Data setup to PCLK active edge
Data hold from PCLK active edge
DE Stop setup to VS start
Vertical Non-Display Period
Note
In 36-bit mode, the data is always guaranteed to be launched on the correct edge of
PCLK. In this mode, the frequency of PCLK is ½ the programmed internal value. If it is
desired that HS and VS are always launched on the same edge of PCLK as the data, then
HNDP, HSW, and HSS should be programmed with even values.
Table 7-9: 18/36-Bit TFT A.C. Timing
Parameter
Revision 6.01 - EPSON CONFIDENTIAL
www.DataSheet.co.kr
Min
0.5
0.5
0.5
0.5
0.5
0.5
0.5
—
—
—
—
—
—
—
—
—
—
1
VDISP + VNDP
HDISP + HNDP
HNDP-HPS
HDISP
VNDP
VSW
HSW
HPS
HPS
VPS
Typ
—
—
—
—
—
—
—
—
Max
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
Lines
Lines
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
X63A-A-001-06
S1D13742
Page 39
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