S1D13742 Epson, S1D13742 Datasheet - Page 15

• Manufacturer Part Number: S1D13742
• Description: Mobile Graphics Engine
• Manufacturer: Epson

4.2.2 LCD Interface
Pin Name
VD[35:0]
PCLK
Epson Research and Development
Vancouver Design Center
Hardware Functional Specification
Issue Date: 2007/09/18
VS
HS
DE
Type
IO
O
O
O
O
L3,L4,L5,L6,
J6,J7,J8,J9,
J10,J11,K4,
K8,K9,K10,
F8,F9,F10,
H11,J4,J5,
K5,K6, K7,
E10,E11,
G9,G10,
L7,L8,L9
G11,H8,
H9,H10,
FCBGA
F11,G8,
Pin #
D10
D11
C11
D9
Note
Note
The LCD interface requires a separate power rail (PIOVDD) to support the configurable
IO drive. For details, see the CNF2 description in Section 4.3, “Summary of Configura-
tion Options” on page 18.
Input of VD[35:0] is used for production test only.
13,12,14,15,
16,19,25,24,
23,22,46,26,
27,28,63,60,
57,50,47,43,
29,30,64,61,
58,51,48,44,
42,66,65,62,
59,54,49,45
Pin #
QFP
10
11
Table 4-3: LCD Interface Pin Descriptions
9
8
Revision 6.01 - EPSON CONFIDENTIAL
DSEL
HB_
Cell
HO
HO
HO
HO
PIOVDD
PIOVDD
PIOVDD
PIOVDD
PIOVDD
Voltage
IO
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RESET#
State
CLKI
H
H
L
L
Power
Status
Save
L
L
L
L
L
Panel Data bits 35-0. VD[35:0] are used
for all modes. In 2 pixels/clock mode,
VD[17:0] represent the 1st pixel sent in
a 2 pixel/clock operation.
Note: The Panel Data Lines can be
swapped (i.e. VD23 = VD0) using the
VD Data Swap bit, REG[14h] bit 7.
Note: The VD output drive is selectable
between 2.5mA and 6.5mA using the
CNF2 pin. For details, see Section 4.3,
“Summary of Configuration Options” on
page 18.
This output pin is the Vertical Sync
pulse
This output is the Horizontal Sync pulse
This output pin is the Data Clock
This output pin is the Data Enable
Description
X63A-A-001-06
S1D13742
Page 15
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