MB15E07SR Fujitsu Media Devices, MB15E07SR Datasheet - Page 9
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MB15E07SR
Manufacturer Part Number
MB15E07SR
Description
Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler
Manufacturer
Fujitsu Media Devices
Datasheet
1.MB15E07SR.pdf
(25 pages)
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Table 2. Binary 14-bit Programmable Reference Counter Data Setting
Note: Divide ratio less than 3 is prohibited.
Table 3. Binary 11-bit Programmable Counter Data Setting
Note: Divide ratio less than 3 is prohibited.
Divide ratio (R)
Divide ratio (N)
LSB
C
N
1
T
CNT
N1 to N11: Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
Note: Data input with MSB first.
16383
2047
Programmable Counter
3
4
3
4
⋅
⋅
A
2
1
A
3
2
: Control bit
R14
N11
A
4
3
0
0
1
0
0
1
⋅
⋅
A
5
4
R13
N10
0
0
1
0
0
1
⋅
⋅
A
6
5
R12
N9
0
0
1
⋅
0
0
1
⋅
A
7
6
R11
N8
0
0
1
⋅
0
0
1
⋅
A
8
7
R10
N7
0
0
1
Data Flow
N
⋅
9
1
0
0
1
⋅
10
N
R9
2
0
0
1
N6
⋅
0
0
1
⋅
11
N
3
R8
0
0
1
N5
⋅
0
0
1
⋅
12
N
4
R7
0
0
1
⋅
N4
0
0
1
⋅
13
N
5
R6
0
0
1
⋅
N3
14
0
1
1
N
6
⋅
R5
0
0
1
15
⋅
N
7
N2
1
0
1
⋅
MB15E07SR
R4
16
N
8
0
0
1
⋅
[Table 1]
[Table 3]
[Table 4]
N1
1
0
1
⋅
17
N
9
R3
0
1
1
⋅
18
10
N
R2
1
0
1
⋅
19
11
MSB
N
R1
1
0
1
⋅
9