MB15E07SR Fujitsu Media Devices, MB15E07SR Datasheet - Page 10

• Manufacturer Part Number: MB15E07SR
• Description: Single Serial Input PLL Frequency Synthesizer On-chip 2.5 GHz Prescaler
• Manufacturer: Fujitsu Media Devices

10
MB15E07SR
Table 4. Binary 7-bit Swallow Counter Data Setting
Table 5. Prescaler Data Setting
Table 6. Charge Pump Current Setting
Table 7. LD/fout Output Select Data Setting
(2) Relation between the FC Input and Phase Characteristics
Table 8. FC Bit Data Setting (LDS =
*: High impedance
Divide ratio (A)
The FC bit changes the phase characteristics of the phase comparator. The internal charge pump output level
(D
relationship between the FC bit and D
fr > f
fr < f
fr = f
LDS
O
SW
CS
) is reversed according to the FC bit. Also, the monitor pin (f
1
0
1
0
1
0
127
P
P
P
0
1
⋅
fout signal
LD signal
D
Z*
H
L
O
A7
0
0
1
⋅
FC = 1
A6
fout = fr
LD/fout
0
0
1
⋅
LD/
Prescaler divide ratio
f
OUT
Current value
A5
0
0
1
⋅
±4.0 mA
±1.0 mA
output signal
32/33
64/65
A4
O
0
0
1
“1”)
⋅
D
is shown below.
Z*
H
L
O
FC = 0
A3
0
0
1
⋅
fout = fp
LD/fout
A2
0
0
1
⋅
A1
0
1
1
⋅
OUT
) output is controlled by the FC bit. The