MB15C03 Fujitsu, MB15C03 Datasheet - Page 13

• Manufacturer Part Number: MB15C03
• Description: Single Serial Input PLL Frequency Synthesizer On-Chip prescaler
• Manufacturer: Fujitsu

(4) Setting the divide ratio for the programmable reference divider
Columns R0-R13 of Table 3 represent the divide ratio of the programmable reference counter. The control bit is
set to 1.
(5) Setting data input timing
The MB15C03 uses 20 bits of serial data for the programmable divider and 16 bits for the programmable reference
divider. When more bits of serial data than defined for the target divider are received, only the last valid serial
data bits are effective.
To set the divide ratio for the MB15C03 dividers, it is necessary to supply the Data, Clock, and LE signals at the
timing shown in Figure 5.
t
t
Divide
16383
1
4
ratio
(R)
( 0.5 s): Data setup time
( 0.5 s): LE setup time to the rising edge of last clock
5
6
•
R
0
1
0
1
•
R
1
0
1
1
•
Table.3 Divide ratio for the programmable reference divider
R
2
1
1
1
•
R
3
0
0
1
•
t
2
( 0 5 s): Data hold time
R
4
0
0
1
•
R
5
0
0
1
•
R
6
0
0
1
•
R
7
0
0
1
•
t
t
3
5
R
8
0
0
1
•
( 0.5 s): Clock pulse width
( 0.5 s): LE pulse width
R
9
0
0
1
•
Note: Less than 5 is prohibited.
10
R
0
0
1
•
MB15C03
11
R
0
0
1
•
12
R
0
0
1
•
13
R
0
0
1
•
13