MB15C03 Fujitsu, MB15C03 Datasheet - Page 12

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MB15C03

Manufacturer Part Number
MB15C03
Description
Single Serial Input PLL Frequency Synthesizer On-Chip prescaler
Manufacturer
Fujitsu
Datasheet
12
MB15C03
Table.2.1 Swallow counter divider A
Divide
ratio
(3) Setting the divide ratio for the programmable divider
Columns A0 to A5 of Table.2.1 represent the divide ratio of the swallow counter and columns N0 to N11 of
Table.2.2 represent the divide ratio of programmable counter. The control bit is set to 0.
(A)
63
0
1
Clock
Data
LE
A
0
0
1
1
A
1
0
0
1
Prescaler
A
AND
AND
2
0
0
1
C*
A
3
0
0
1
Table. 2 Divide ratio for the programmable divider
A
4
0
0
1
6-bit binary swallow counter 12-bit binary programmable
A
5
0
0
1
14-bit binary programmable reference counter
Figure 4 The flow of serial data
Divide
ratio
4095
(N)
5
6
6
18-bit shift register
14-bit latch
N
0
1
0
1
Table.2.2 Programmable counter divider N
18-bit latch
N
1
0
1
1
14
14
18
N
2
1
1
1
N
3
0
0
1
counter
N
4
0
0
1
12
N
5
0
0
1
Note: Less than 5 is prohibited.
* : Control register
N
6
0
0
1
N
7
0
0
1
Programmable
reference divider
Programmable
N
8
0
0
1
divider
N
9
0
0
1
10
N
0
0
1
11
N
0
0
1

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