P10C68 GEC Plessey Semiconductors, P10C68 Datasheet - Page 6
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P10C68
Manufacturer Part Number
P10C68
Description
CMOS / SNOS NVSRAM
Manufacturer
GEC Plessey Semiconductors
Datasheet
1.P10C68.pdf
(17 pages)
www.DataSheet4U.com
P10C68/P11C68
WRITE CYCLE 1 : W (BAR) CONTROLLED (See notes 8 and 13)
NOTES
13.
14.
6
Standard
t
t
t
t
t
t
t
t
t
DQ (DATA OUT)
t
WLWH
DVWH
WHDX
WHQZ
ELWH
AVWH
WHAX
WLQZ
AVWL
AVAV
Commercial and Industrial Temperature Range
E (bar) or W (bar) must be ≥ VIH during address transitions.
If W (bar) is low when E (bar) goes low, the outputs remain in the high impedance state.
ADDRESS
I
Symbol
CC
G
E
W
STANDBY
ACTIVE
Alternative
t
t
t
t
t
t
t
t
t
t
OW
WC
WP
CW
DW
AW
WR
WZ
DH
AS
Write cycle time
Write pulse width
Chip enable to end of write
Data set-up to end of write
Data hold after end of write
Address set-up to end of write
Address set-up to start of write
Address hold after end of write
Write enable to output disable
Output active after end of write
F
t
ELICCH
t
WHQV
Parameter
t
ELQX
t
t
GLQV
GLQX
t
t
ELQV
AVAV
Min.
45
35
35
30
35
P10C68-35
P11C68-35
0
0
0
5
Max.
35
Min.
45
35
35
30
35
P10C68-45
P11C68-45
0
0
0
5
DATA VALID
t
GHQZ
Max.
35
t
EHQZ
Units
t
EHICCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
11, 14