CS6652 Amphion, CS6652 Datasheet - Page 3

• Manufacturer Part Number: CS6652
• Description: 2-stream Video Decoder
• Manufacturer: Amphion

Table 2 gives the descriptions of the input and output ports
(shown graphically in Figure 2) of the CS6652 MPEG-2
multistream video decoder. Unless otherwise stated, all
signals are active high and bit(0) is the least significant bit.
Global Signals
Clk
notReset
CoreReset
Elementary Stream Input Interface
ES_Data
ES_Valid
ES_Stall
ES_Select
CS6652/CS6654 SYMBOL AND PIN
Signal
DESCRIPTION
1 or 2
Width
1
1
1
8
1
1
Table 2: CS6652/54 Interface Signal Definitions
Output
Output
Input
Input
Input
Input
Input
I/O
Core clock Master clock used for all logic and the external SDRAM interface. This clock
should also be routed to the external SDRAM chips. The clock is 133MHz
Core reset Asynchronous, active low global core reset.
Core reset Synchronous, active high core reset.
Elementary Stream Data, byte aligned video elementary stream bytes from the Condi-
tional Access decryption core or transport stream demux. Maximum average input bit
rate is 300Mbits/s
Data Valid Strobe, ES_Data is latched on the positive edge of Clk when ES_Valid is
asserted and ES_Stall is not asserted.
Data Stall, input data may be burst into the core at a rate higher than the specified max-
imum 300Mbits/s. In this case the core will indicate that it temporarily cannot receive
any more data by assertion of ES_Stall. ES_Data and ES_Valid will be ignored while
ES_Stall is asserted.
Elementary Stream Select, either a 1-bit (CS6652) or 2-bit (CS6654) signal represent-
ing the number of the elementary stream which the core is currently accepting and
decoding via ES_Data. This signal may be used to drive a mux to switch the correct
elementary stream into the core when selected.
Figure 2: CS6652 Symbol
ES_Select
ES_Valid
ES_Stall
ES_Data[7:0]
H_DataIn[31:0]
H_DataOut[31:0]
H_notDatDrv
H_Addr[21:0]
H_notRegCS
H_notWrite
H_notIRQ
H_notMemRead
H_notMemWrite
H_MemBusy
H_ByteEnable[3:0]
H_MemRdValid
H_MemRdStrb
H_MemWrValid
H_MemWrReady
Description
Clk
notReset
CS6652
CoreReset
P_DataType_0[3:0]
P_DataType_1[3:0]
P_RowDoneOut_0
P_RowDoneOut_1
SD_DataOut[63:0]
P_General_0[7:0]
P_General_1[7:0]
P_PicDoneOut_0
P_PicDoneOut_1
P_RowDoneIn_0
P_RowDoneIn_1
SD_DataIn[63:0]
P_DataStrobe_0
P_DataStrobe_1
P_Data_Avail_0
P_PicDoneIn_0
P_PicDoneIn_1
P_Data_0[15:0]
P_Data_1[15:0]
SD_Addr[10:0]
P_DataAvail_1
SD_notDatDrv
SD_DQM[7:0]
SD_notRAS
SD_notCAS
SD_BA[1:0]
SD_notWE
SD_notCS
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