CS6350 Amphion, CS6350 Datasheet - Page 4

• Manufacturer Part Number: CS6350
• Description: Inverse DCT (Decoder)
• Manufacturer: Amphion

DCT OPERATION
The processing may begin by supplying 8x8 blocks of 11-bit
DCT coefficients to the DctCoef port, with the first sample of
the block being coincident with the DctStrb.
The IDCT is performed as two one dimensional IDCTs, with
the intermediate results being stored in the Transpose
memory. In this high performance IDCT, two processing
blocks comprising multipliers and accumulators are used for
both the one dimensional computation stages of 2D-IDCT. The
output from the first stage is stored in the Transpose Memory
and appropriately supplied to the second stage. Once the
complete 8x8 block has been processed, the IDctRdy signal is
asserted to indicate that the core can now read the next block
of data. The start of each output block is indicated by the
assertion of PixOutSob signal which coincides with the first
output sample at the PixOut port.
There is a latency of 83 clock cycles before which the first
output sample appears at the output. Consequently, there is a
similar latency of 83 CLK cycles between the last input data
Figure 4: IDCT Timing
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CS6350
PixOutValid
DctStrb
IDctRdy
PixOutSob
PixOut
CLK
DctCoef
LATENCY IN THE DESIGN
63
0
High Performance IDCT
1
2
3
System Latency
63
0
1
2
and the last output data. The latency is depicted in the
functional timing diagram in Figure 4.
I/O FUNCTIONAL TIMING DIAGRAMS
The timing diagram in Figure 4 depicts the activities at
various ports for IDCT operation. The start of the block is
marked by DctStrb pulse which remains active for one clock
period. After 83 clock cycles, i.e. system latency, the
PixOutSob goes high to mark the start of new output data
block at PixOut port. The processing of two contiguous input
blocks can be delayed by delaying the assertion of DctStrb
signal. The IDctRdy signal, which shows that the core is ready
for processing, will remain asserted until the core starts to
read a new data block. The core will start processing the data
when DctStrb is asserted. All input signals are sampled with
CLK and all outputs are updated with CLK. Any gaps at the
input DctCoef port are replicated at the output PixOut port
after the latent period. The PixOutValid pin remains asserted
at '1' as long as a valid data is available at the PixOut port. The
core is capable of performing consecutive IDCT with or
without gaps between successive input blocks.
0
19
1
20
2
63
0
19
1
20
63