CS6350 Amphion, CS6350 Datasheet - Page 3

• Manufacturer Part Number: CS6350
• Description: Inverse DCT (Decoder)
• Manufacturer: Amphion

FUNCTIONAL DESCRIPTION
The DCT is a transform that converts a signal into its
constituent frequency components as represented by a set of
coefficients. For an image, this transform is performed on a 2
dimensional array of samples, resulting in a 2 dimensional
array of coefficients. The data input into the core and output
from the core takes place as a block of 8x8 samples. In the case
of IDCT, the input to the core is the block of transformed
coefficients and the output is the original pixels.
process. The two-stage process performs the transform as two
separate one-dimensional transforms. This results in a set of
intermediate results being produced which require storage
and further processing.
The CS6350 performs its function as two 1-dimensional
transforms, using row-column decomposition, with the
intermediate results being stored in the transpose memory. A
block diagram of the core, showing the main interfaces and
functional blocks is shown in Figure 3 with the blocks
described in the following sections.
Figure 3: IDCT Block Diagram
The core is initialized on power-up by an asynchronous active
low pulse at RSTn port or a synchronous active high pulse at
CLR port. Data is burst into the core in blocks of 64, with the
first data value being accompanied by DctStrb signal. The core
accepts 11-bit DCT coefficient inputs and produces an 8-bit
pixel data output.
This processing stage comprises a multiplier-accumulator unit
as well as a Cosine lookup tables for respective IDCT
computations. The input to this stage is the data DctCoef from
the input port. The output from this processing stage is
rounded to 15-bits to provide the desired computational
accuracy and passed onto the transpose memory.
The transform can be performed as a one or two stage
CS6350
DctStrb
DctCoef
CLK
CLR
RSTn
Stage 1
STAGE 1
Transpose
Memory
Stage 2
PixOut
PixOutSob
IDctRdy
PixOutValid
This processing stage comprises a multiplier-accumulator unit
as well as a Cosine lookup tables for respective IDCT
computations. The input to this stage is the data stored in the
Transpose Memory by stage 1. This stage, similar to stage1,
performs a 1-D IDCT and provides the final 8-bit output at
PixOut port.
This 64x15 dual-port RAM stores intermediate results after
first stage of processing. The data is written into the memory
in a row-major order and read from it in a column-major
order, which is effectively a transposition. Along with the
transposition of data, it provides input to the processing stage
for the second stage of IDCT processing
The core implements the 2-D IDCT as two one-dimensional
operations as defined by the following equations. The results
from the first stage are stored in the transpose memory.
DCT
IDCT
where
The Amphion implementation performs the transform in two
stages with the first stage results being stored in the Transpose
memory. The width of this memory, 15-bit, controls the
number of fractional bits stored and hence influences the
accuracy of the final result. The other factor that controls the
accuracy is the number of fractional bits, i.e. 14-bits, used
when calculating the cosine coefficients.
C u ( )
C u ( )
s x ( ) = 1-D sample value
S u ( ) = 1-D DCTcoefficient
S u ( )
S u ( )
=
=
------ -
1
=
=
1
TRANSPOSE MEMORY
2
C u ( )
----------- -
C u ( )
----------- -
2
2
for u=0
for u>0
x
x
∑
∑
ALGORITHM
=
=
7
7
ACCURACY
0
0
s x ( )
S u ( )
STAGE 2
cos
cos
(
-------------------------- -
(
-------------------------- -
2x
2x
+
16
+
16
1
1
)uπ
)uπ
3
TM