CS3110 Amphion, CS3110 Datasheet - Page 4

• Manufacturer Part Number: CS3110
• Description: Reed-solomon RS Encoder (DVB)
• Manufacturer: Amphion

Before operation of the encoder can commence, the code generator polynomial coefficients, the codeword length and the parity
length must be loaded into their appropriate registers via the processor interface. The addresses of the respective registers are
given in Table 2.
Addresses 00
polynomial coefficients, while address 1F
codeword length value (in symbols) and address 1F
contains the parity length value. Every time the parity length
changes, its value and the values of the appropriate generator
coefficients must be loaded into their registers before error-
free encoding can commence. Values are loaded into their
respective registers by applying the correct address signal to
Add, the parameter values to UP_Din and then asserting the
write enable signal. The inputs Add and UP_Din are sampled
on the write signal WR rising edge. The contents of the
registers can be read by applying the correct address signal to
Add and asserting the read enable signal RD. The contents are
loaded to UP_Dout on the read signal RD rising edge.
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CS3110/12
ADDRESS
(HEX)
0A
0B
00
01
02
03
04
05
06
07
08
09
HEX
Generator Coefficient (10)
Generator Coefficient (11)
Generator Coefficient (0)
Generator Coefficient (1)
Generator Coefficient (2)
Generator Coefficient (3)
Generator Coefficient (4)
Generator Coefficient (5)
Generator Coefficient (6)
Generator Coefficient (7)
Generator Coefficient (8)
Generator Coefficient (9)
– 13
HEX
Table 2: Register Address Contents for Microprocessor Interface
CONTENT
contain the code generator
Reed-Solomon Encoders
PROCESSOR INTERFACE
HEX
contains the
CONTENT
WIDTH
(bits)
8
8
8
8
8
8
8
8
8
8
8
8
HEX
All synchronous elements in the encoders are clocked using
the rising edge of the Clk signal. The exceptions to this are the
registers holding the generator polynomial coefficients,
codeword length and parity length. These are written and
read using strobe signals present in the processor interface.
Additionally, all I/O signals are registered on the rising edge
of Clk, with the exception of Reset. When the reset signal
Reset is asserted, all registers will be set to zero value. The
codeword length register will be loaded with the value FF
(255
value 10
are loaded with the corresponding coefficients for the given
parity length. The default code rate is therefore (255, 239).
ADDRESS
(HEX)
14-1D
RESET AND CLOCKING STRATEGY
10
OC
OD
OE
OF
1E
1F
10
11
12
13
) and the parity length register will be loaded with the
HEX
(16
Codeword Length (symbols)
10
Generator Coefficient (12)
Generator Coefficient (13)
Generator Coefficient (14)
Generator Coefficient (15)
Generator Coefficient (16)
Generator Coefficient (17)
Generator Coefficient (18)
Generator Coefficient (19)
). The code generator polynomial registers
Parity Length (symbols)
CONTENT
Reserved
CONTENT
WIDTH
(bits)
8
8
8
8
8
8
8
8
x
8
5
HEX