FW912 Micron Semiconductor Products, FW912 Datasheet - Page 35

• Manufacturer Part Number: FW912
• Description: Flash Memory Technology
• Manufacturer: Micron Semiconductor Products

ASYNCHRONOUS PAGE READ MODE
mode over the whole memory array. The page size can
be customized at the factory to four or eight words as
required; but if no specification is made, the normal
size is eight words. The initial portion of the page mode
cycle is the same as the asynchronous access cycle.
Holding CE# LOW and toggling addresses A0–A2 al-
lows random access of other words in the page.
V
VOLTAGES
and erase with V
mode programming is offered for compatibility with
existing programming equipment, and it allows the
APA execution as well.
operations, irrespective of the external V
cause the memory cells are always programmed using
the internal power sources. This provides an optimal
voltage profile in order to minimize the programming
stress.
gramming voltage can be held LOW for absolute hard-
ware write protection of all blocks in the Flash device.
When V
eration will result in an error, prompting the correspond-
ing status register bit (SR3) to be set.
monitors the V
tions are allowed only when V
specified in Table 14.
tion will be disabled.
STANDBY MODE
HIGH level on CE# and RST# to enter the standby
mode. In the standby mode, the outputs are High-Z.
Applying a CMOS logic HIGH level on CE# and RST#
reduces the current to I
lected during an ERASE operation or during program-
4 Meg x 16 Async/Page/Burst Flash Memory
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
PP
After power-up or reset, the device operates in page
The Flash devices provide in-system programming
The device can withstand 100,000 WRITE/ERASE
In addition to the flexible block locking, the V
During WRITE and ERASE operations, the WSM
When V
I
CC
/V
In Factory
In System
CC
supply current is reduced by applying a logic
PP
PROGRAM AND ERASE
is below V
CC
is below V
PP
PP
V
voltage level. WRITE/ERASE opera-
in the 0.9V–2.20V range. The 12V V
PP
PPLK
Table 14
Range (V)
CC
, any PROGRAM or ERASE op-
LKO
4
MIN
11.4
0.9
(MAX). If the device is dese-
, any WRITE/ERASE opera-
PP
is within the ranges
PP
MAX
applied be-
12.6
2.2
PP
pro-
PP
ASYNC/PAGE/BURST FLASH MEMORY
35
ming, the device continues to draw current until the
operation is complete.
AUTOMATIC POWER SAVE (APS) MODE
ods when the array is not being read and the device is in
the active mode. During this time the device switches
to the automatic power save mode. When the device
switches to this mode, I
rable to I
applying a logic HIGH level on CE# to place the device
in standby mode. The low level of power is maintained
until another operation is initiated. In this mode, the
I/Os retain the data from the last memory address read
until a new address is read. This mode is entered auto-
matically if no address or control signals toggle.
DEVICE RESET
must be asserted (RST# = V
After reset, the device can be accessed for a READ op-
eration with a delayed access time of
rising edge of RST#. RST# should be tied to the system
reset to ensure that correct system initialization occurs.
Please refer to the timing diagram for further details.
DEEP POWER-DOWN
In this configuration, applying a logic LOW to RST#
reduces the current to I
registers, with the exception of the RCR and the indi-
vidual block protection status. To exit this mode, a wait
time of 100µs (
is applied to RST#.
power-up sequence, and the power consumption may
exceed the standby current limits.
POWER-UP SEQUENCE
to initialize internal chip operations:
should be brought to V
the rise time of RST# (10%–90%) should be < 10µs.
Substantial power savings are realized during peri-
To correctly reset the Flash devices, the RST# signal
During the wait time, the device performs a full
The following power-up sequence is recommended
• At power-up, RST# should be kept at V
• V
• V
When the power-up sequence is completed, RST#
When RCR4 = 1, deep power-down can be enabled.
after V
integrity.
CC
PP
Q should not come up before V
CC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
should be kept at V
4
. Further power savings can be realized by
CC
t
RWHDP) must elapse after a logic HIGH
reaches V
IH
CC
CC
. To ensure a proper power-up,
CC
10
is reduced to a level compa-
(MIN).
IL
and resets all the internal
) for a minimum of
IL
4 MEG x 16
to maximize data
t
©2002, Micron Technology, Inc.
RWH from the
CC
ADVANCE
.
IL
for 2µs
t
RP.