IS61C25616AL Integrated Silicon Solution, Inc., IS61C25616AL Datasheet - Page 10

• Manufacturer Part Number: IS61C25616AL
• Description: 256k X 16 High-speed Cmos Static Ram
• Manufacturer: Integrated Silicon Solution, Inc.

IS61C25616AL
IS64C25616AL
WRITE CYCLE NO. 3
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE
10
WRITE CYCLE NO. 2
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
ADDRESS
UB, LB
UB, LB
D
D
OUT
WE
D
OE
OUT
CE
WE
D
OE
CE
IN
IN
LOW
LOW
IS61C25616AS
IS64C25616AS
LOW
(OE is LOW During Write Cycle)
(OE is HIGH During Write Cycle)
t
SA
t
DATA UNDEFINED
DATA UNDEFINED
SA
≥
V
IH
.
VALID ADDRESS
t
t
t
t
AW
HZWE
AW
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
t
WC
t
PBW
PBW
(1)
(1,2)
HIGH-Z
HIGH-Z
t
t
Integrated Silicon Solution, Inc. — www.issi.com
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
UB_CEWR2.eps
UB_CEWR3.eps
03/21/2008
Rev. C