MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 41

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

40
MBM29QM12DH
DQ
Data Polling
DQ
Toggle Bit I
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce a
complement of data last written to DQ
read the device will produce true data last written to DQ
rising edge of the fourth write pulse in the four write pulse sequences. During the Embedded Erase Algorithm,
an attempt to read the device will produce a “0” at the DQ
Algorithm, an attempt to read device will produce a “1” on DQ
in “Temporary Sector Group Unprotection Algorithm” in “ FLOW CHART”.
Data polling will also flag the entry into Erase Suspend. DQ
mode. Please note that the address of an erasing sector must be applied in order to observe DQ
Suspend Mode.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequences. Data Polling must be performed at sector addresses of sectors being erased, not pro-
tected sectors. Otherwise the status may become invalid.
If a program address falls within a protected sector, Data Polling on DQ
that bank returns to the read mode. After an erase command sequence is written, if all sectors selected for
erasing are protected, Data Polling on DQ
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
asynchronously while the output enable (OE) is asserted low. This means that device is driving status information
on DQ
the DQ
operation and DQ
DQ
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See “Hardware Sequence Flags Table” in “ COMMAND DEFINITION”.)
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in “ TIMING DIAGRAM” for the Data
Polling timing specifications and diagrams.
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from the
busy bank will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse
sequences. For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse
in the six write pulse sequences. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1 s and then stop
toggling with data unchanged. In erase, the device will erase all selected sectors except for protected ones. If
all selected sectors are protected, the chip will toggle the toggle bit for about 400 µs and then drop back into
read mode, having data kept remained.
Either CE or OE toggling will cause DQ
DQ
The system can use DQ
is actively erased (that is, the Embedded Erase Algorithm is in progress) , DQ
Erase Suspend mode, DQ
to toggle.
7
6
7
6
will be read on successive read attempts.
to toggle.
7
7
at one instant, and then that byte’s valid data at the next instant. Depending on when the system samples
output, it may read the status or valid data. Even if device has completed the Embedded Algorithm
7
has a valid data, data outputs on DQ
6
6
will stop toggling and valid data will be read on the next successive attempts. During
to determine whether a sector is actively erased or is erase-suspended. When a bank
6
6
stops toggling. Successive read cycles during erase-suspend-program cause DQ
toggling between one and zero. Once the Embedded Program or Erase Algorithm
-60
7
6
. Upon completion of the Embedded Program Algorithm, an attempt to
to toggle. In addition, an Erase Suspend/Resume command will cause
7
is active for approximately 400 s, then the bank returns to read mode.
7
0
. For programming, the Data Polling is valid after the
7
to DQ
7
will switch “0” to “1” at the start of the Erase Suspend
output. Upon completion of the Embedded Erase
7
. The flowchart for Data Polling (DQ
6
may still be invalid. The valid data on DQ
7
is active for approximately 1 s, then
6
toggles. When a bank enters the
7
) may change
7
in the Erase
7
) is shown
0
to
6