MBM29QM12DH Fujitsu Microelectronics, Inc., MBM29QM12DH Datasheet - Page 27

• Manufacturer Part Number: MBM29QM12DH
• Description: Page Mode Flash Memory 128m 8m X 16 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

26
MBM29QM12DH
Automatic Sleep Mode
Output Disable
Autoselect
Write
Accelerated Program Operation
Automatic sleep mode works to restrain power consumption during read-out of device data. It can be useful in
applications such as handy terminal, which requires low power consumption.
To activate this mode, the device automatically switches itself to low power mode when the device addresses
remain stable during access time of 150 ns. It is not necessary to control CE, WE and OE in this mode. In this
mode the current consumed is typically 1 µA (CMOS Level) .
During simultaneous operation, V
Since the data are latched during this mode, the data are continuously read out. When the addresses are
changed, the mode is automatically canceled and the device reads the data for changed addresses.
With the OE input at a logic high level (V
to be in a high impedance state.
The Autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.It is intended
for use by programming equipment for the purpose of automatically matching the device to be programmed with
its corresponding programming algorithm. This mode is functional over the entire temperature range of the device.
To activate this mode, the programming equipment must force V
then be sequenced from the device outputs by toggling addresses. All addresses are DON’T CARES except A
A
mand Definitions Table” in “ DEVICE BUS OPERATION”.)
The manufacturer and device codes may also be read via the command register, for instances when the device
is erased or programmed in a system without access to high voltage on the A
illustrated in “MBM29QM12DH Command Definitions Table” in “
toselect Command section.)
In the command Autoselect mode, the bank addresses BA;(A
the third write bus cycle of the Autoselect command. Then the Autoselect data will be read from that bank while
array data can be read from the other bank.
In WORD mode, a read cycle from address 00h returns the manufacturer’s code (Fujitsu
at address 01h outputs device code. When 227Eh is output, it indicates that two additional codes, called Extended
Device Codes will be required. Therefore the system may continue reading out these Extended Device Codes
at addresses of 0Eh and 0Fh. (Refer to “MBM29QM12DH Sector Group Protection Verify Autoselect Codes
Table” and “Extended Autoselect Code Table” in “ DEVICE BUS OPERATION” )
In the case of applying V
cannot be executed.
Device erasure and programming are accomplished via the command register. The contents of the register serve
as input to the internal state machine. The state machine output dictates the function of the device.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to V
falling edge of WE or CE, whichever happens later, while data is latched on the rising edge of WE or CE, whichever
happens first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
The device offers accelerated program operation which enables the programming in high speed. If the system
asserts V
6
, A
5
, A
4
, A
ACC
3
, A
to the WP/ACC pin, the device automatically enters the acceleration mode and the time required
2
, A
1
and A
ID
0
on A
. (See “MBM29QM12DH User Bus Operations Table” and “MBM29QM12DH Com-
9
, since both Bank 1 and Bank 2 enter Autoselect mode, simultanous operation
-60
CC
active current (I
IH
) , output from the device is disabled. This will cause the output pins
IL
, while CE is at V
CC2
) is required.
IL
22
ID
, A
and OE is at V
on address pin A
21
DEVICE BUS OPERATION”. (Refer to Au-
, A
20
) must point to a specific bank during
9
IH
pin. The command sequence is
. Addresses are latched on the
9
. Three identifier bytes may
04h) . A read cycle
7
,