MBM29PL3200BE Fujitsu Microelectronics, Inc., MBM29PL3200BE Datasheet - Page 28

• Manufacturer Part Number: MBM29PL3200BE
• Description: Page Mode Flash Memory 32 M 2 M X 16/1 M X 32 Bit
• Manufacturer: Fujitsu Microelectronics, Inc.

28
MBM29PL3200TE/BE
DQ
Data Polling
DQ
Toggle Bit I
The device features Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm an attempt to read the device will produce a
complement of data last written to DQ
read the device will produce true data last written to DQ
read the device will produce a “0” at the DQ
attempt to read the device will produce a “1” on DQ
For programming, the Data Polling is valid after the rising edge of the fourth write pulse in the four write pulse
sequence.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. Data Polling must be performed at the sector address of sectors being erased, not
protected sectors. Otherwise, the status may be invalid.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
asynchronously while the output enable (OE) is asserted low. This means that the device is driving status
information on DQ
the system samples the DQ
Embedded Algorithm operation and DQ
valid data on DQ
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algorithm
or sector erase time-out. (See Table 10.)
See Figure 9 for the Data Polling timing specifications and diagrams.
The device also features the “Toggle Bit I” as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
During the Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device will result in DQ
cycle is completed, DQ
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write pulse sequence.
For chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six
write pulse sequence. The Toggle Bit I is active during the sector time out.
In programming, if the sector being written is protected, the toggle bit will toggle for about 1 s and then stop
toggling with data unchanged. In erase, device will erase all selected sectors except for ones that are protected.
If all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into
read mode, having data unchanged.
Either CE or OE toggling will cause DQ
DQ
See Figure 10 and Figure 20 for the Toggle Bit I timing specifications and diagrams.
7
6
6
to toggle.
7
7
to DQ
at one instant and then that byte’s valid data at the next instant of time. Depending on when
6
0
will stop toggling and valid data will be read on the next successive attempts. During
will be read on successive read attempts.
6
7
toggling between one and zero. Once the Embedded Program or Erase Algorithm
output, it may read the status or valid data. Even if the device has completed the
7
6
. Upon completion of the Embedded Program Algorithm, an attempt to
7
to toggle. In addition, an Erase Suspend/Resume command will cause
has valid data, data outputs on DQ
70/90
7
output. Upon completion of the Embedded Erase Algorithm an
7
. The flowchart for Data Polling (DQ
7
. During the Embedded Erase Algorithm, an attempt to
6
to DQ
0
7
may be still invalid. The
) is shown in Figure 19.
7
) may change