OM6206 NXP Semiconductors, OM6206 Datasheet - Page 6

• Manufacturer Part Number: OM6206
• Description: 65 X 102 Pixels Matrix Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6.1.9
Input for the data line.
6.1.10
Input for the clock signal: up to 4.0 Mbits/s.
6.1.11
Input to select either command or address data input.
6.1.12
The enable pin allows data to be clocked in. Signal is
active LOW.
6.1.13
When the on-chip oscillator is used this input must be
connected to V
connected to this input. If the oscillator and external clock
are both inhibited by connecting pin OSC to V
display is not clocked and may be left in a DC state. To
avoid this the chip should always be put into
Power-down mode before stopping the clock.
6.1.14
This signal will reset the device and must be applied to
properly initialize the chip. Signal is active LOW.
7
7.1
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC input must be connected to V
clock signal, if used, is connected to this input.
2001 Nov 14
65
FUNCTIONAL DESCRIPTION
Oscillator
SDIN:
SCLK:
D/C:
SCE:
OSC:
RES:
102 pixels matrix LCD driver
MODE SELECT
CHIP ENABLE
RESET
DD
OSCILLATOR
SERIAL DATA LINE
SERIAL CLOCK LINE
. An external clock signal, if used, is
DD
. An external
SS
, the
6
7.2
The address counter assigns addresses to the display
data RAM for writing. The X-address X
Y-address Y
operation, the address counter is automatically
incremented by 1 according to bit V (see Section 7.7).
7.3
The OM6206 contains a 65
stores the display data. The RAM is divided into
eight banks of 102 bytes (8
of 102 bits (1
transferred to the RAM via the serial interface. There is a
direct correspondence between X-address and column
output number.
7.4
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not affected by operations on the data bus.
7.5
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits E and D in the command ‘Display
control’ (see Table 2).
7.6
The OM6206 contains 65 rows and 102 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 2 shows typical waveforms. Unused
outputs should be left unconnected.
Address counter
Display Data RAM (DDRAM)
Timing generator
Display address counter
LCD row and column drivers
3
to Y
102 bits). During RAM access, data is
0
are set separately. After a write
8
102 bits static RAM which
102 bits) and one bank
Product specification
6
to X
OM6206
0
and the