OM6208 NXP Semiconductors, OM6208 Datasheet - Page 49

• Manufacturer Part Number: OM6208
• Description: Om6208 65 X 96 Pixels Matrix Grey-scale Lcd Driver
• Manufacturer: NXP Semiconductors

Philips Semiconductors
17.4.1
The OTP architecture allows the following operations:
The reading of data from the OTP cells is initiated by
writing to the DON register. The OTP cells will not be
updated until the device leaves power down and the
oscillator starts. The reading operation needs up to 5 ms
to complete.
Table 23 OTP bit order (See Fig.44 for a graphical representation)
2003 feb 10
Reading data from the OTP cells. The content of the
non-volatile OTP cells is transferred to the shift register
where upon it may affect the OM6208 operation.
Writing data to the OTP cells. First, all 9 bits of data are
shifted into the shift register via the interface. Then the
content of the shift register is transferred to the OTP
cells (there are some limitations related to storing data
in these cells, see Section 17.7).
Checking calibration without writing to the OTP cells.
Shifting data into the shift register allows the effects on
the V
65 x 96 pixels matrix grey-scale LCD driver
POSITION
LCD
10
11
12
13
14
15
16
17
18
OTP
1
2
3
4
5
6
7
8
9
voltage to be observed.
OPERATIONAL EFFECTS
OTP CELL
MMVPR[7]
MMVPR[6]
MMVPR[5]
MMVPR[4]
MMVPR[3]
MMVPR[2]
MMVPR[1]
MMVPR[0]
MMSLD[2]
MMSLD[1]
MMSLD[0]
MMSLC[2]
MMSLC[1]
MMSLC[0]
MMSLB[2]
MMSLB[1]
MMSLB[0]
MMSLA[2]
POSITION
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
49
The shifting of the data into the shift register is performed
in the special mode CALMM. In the OM6208, the CALMM
mode is entered through the CALMM command. Once in
the CALMM mode the data is shifted into the shift register
via the interface at the rate of 1-bit per command. After
transmitting the last bit and exiting the CALMM mode the
serial interface is again in the normal mode and all other
commands can be sent. Care should be taken that always
all bits of data (or a multiple of all bits) are transferred
before exiting the CALMM mode, otherwise the bits will be
in the wrong positions.
In the shift register the value of the seal bit is, like the other
bits, always zero at reset. To make sure the security
feature works correctly, the CALMM command is disabled
until a Power-down mode has been left. Once a refresh is
completed, the seal bit value in the shift register is valid
and permission to enter CALMM mode can thus be
determined.
The bits are shifted into the shift register in a predefined
order as shown in Table 23.
MMVOPCAL[5]
MMVOPCAL[4]
MMVOPCAL[3]
MMVOPCAL[2]
MMVOPCAL[1]
MMVOPCAL[0]
OTP CELL
MMGFR[2]
MMGFR[1]
MMGFR[0]
MMSLA[1]
MMSLA[0]
MMGT[2]
MMBS[2]
MMBS[1]
MMBS[0]
MMS[1]
MMS[0]
MMFD
POSITION
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
Product specification
OM6208
OTP CELL
MMSFR[2]
MMSFR[1]
MMSFR[0]
MMGT[1]
MMGT[0]
MMST[2]
MMST[1]
MMST[0]
MMNL[6]
MMNL[5]
MMNL[4]
MMNL[3]
MMNL[2]
MMNL[1]
MMNL[0]
MMFI
SEAL