MTV038 ETC-unknow, MTV038 Datasheet - Page 13

• Manufacturer Part Number: MTV038
• Description: On-screen Display Controller For Crt/lcd Monitor
• Manufacturer: ETC-unknow

RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up.
BSEN - Enable the bordering and shadowing effect.
SHADOW - Bordering and shadowing effect select bit. Activate the shadowing effect if this bit is set, otherwise
FBEN - Enable the fade-in/fade-out and blending-in/blending-out effect when OSD is turned on from off state
BLEND - Fade-in/fade-out and blending-in/blending-out effect select bit. Activate the blendinf-in/blending-out
WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after
RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set
FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs high during the
(SELVCL, VCO1, VCO0 bits are used only for CRT monitor application.)
(DWE bit is used only for LCD monitor application.)
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is,
FSS - Font size selection.
SELVCL - Enable auto detection for horizontal and vertical syncs input edge distortion to avoid unstable
Revision 1.1
Column 16
Column 17
Column 18
while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are
in high impedance state. The initial value is 0 after power up.
= 1 -> 12x18 font size selected.
= 0 -> 12x16 font size selected.
or vice versa.
function if this bit is set, otherwise the fade-in/fade-out function is chosen. These function roughly
takes about 0.5 second to fully display the whole menu or to disappear completely.
displaying of characters or windows, otherwise, it outputs high only during the displaying of charac-
ter.
to "1". The initial value is 0 after power up.
Vsync leading mismatch with Hsync signal while the bit is set to "1". The initial value is 0 after
power up.
be appended below each display row, and the maximum space is 31 lines. The initial value is 0
after power up.
power up.
the bordering is chosen.
OSDEN
TRIC
b7
B7
MYSON
TECHNOLOGY
-
b7
b6
FSS
-
BSEN
b6
b6
b5
-
SHADOW
b5
-
MSB
b5
b4
SELVCL/DWE
FBEN
b4
b3
b4
-13-
RSPACE
BLEND
b2
b3
HSP
b3
b1
WENCLR
VSP
b2
b2
b0
LSB
VCO1/- VCO0/-
(Revision 1.1)
RAMCLR
b1
b1
b0
MTV038
FBKGC
b0
2001/8/21