MTV038 ETC-unknow, MTV038 Datasheet

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MTV038

Manufacturer Part Number
MTV038
Description
On-screen Display Controller For Crt/lcd Monitor
Manufacturer
ETC-unknow
Datasheet

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BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice.
No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product.
Revision 1.1
FEATURES
• Horizontal SYNC input up to 150 KHz.
• On-chip PLL circuitry or external pixel clock input up to
• Software control for CRT/LCD applications.
• Programmable R,G,B input level for timing measurement
• Full screen self-test pattern generator.
• Programmable Hor. resolutions up to 1524 dots per line.
• Full-screen display consists of 15 (rows) by 30 (columns)
• Two font size 12x16 or 12x18 dot matrix per character.
• True totally 544 mask ROM fonts including 512 standard
• Character button boxes with programmable box length.
• Double character height and/or width control.
• Programmable positioning for display screen center.
• Character bordering, shadowing and blinking effect.
• Character (per row) and window intensity control .
• Row to row spacing control to avoid expansion distortion.
• 4 programmable windows with multi-level operation.
• Shadowing on windows with programmable shadow
• Programmable adaptive approach to handle H, V sync
• Software clears bit for full-screen erasing.
• Fade-in/fade-out or blending-in/blending-out effects.
• Compatible with SPI bus or I
• 16-pin or 20-pin PDIP/SOP package.
150 MHz.
among HFLB, VFLB, RIN, GIN and BIN for auto sizing.
fonts and 32 multi-color fonts.
width/height/color.
collision automatically by hardware.
address 7AH/7BH (slave address is mask option).
On-Screen Display Controller for CRT/LCD Monitor
VFLB
HFLB
VCO
SSB
SCK
SDA
GIN
RIN
BIN
RP
MYSON
TECHNOLOGY
VSP
HSP
VERTD
ARWDB
HORD 8
HDREN
VDREN
NROW
CHS
CH
7
8
2
C interface with slave
DISPLAY CONTROL
PHASE LOCK LOOP
ADMINISTRATOR
MEASUREMENT
SERIAL DATA
ADDRESS BUS
AUTO SIZING
INTERFACE
HORIZONTAL
CONTROL
VERTICAL
DISPLAY
5
8
9
ARWDB
HDREN
VCLKX
DATA
ROW, COL
ACK
5
9
9
5
5
LPN
NROW
VDREN
8
RCADDR
DADDR
FONTADDR
WINADDR
PWMADDR
DATA
-1-
VCLKS
8
8
7
DATA
GENERAL DESCRIPTION
to display built-in characters or fonts onto monitor screens.
The display operation occurs by transferring data and con-
trol information from the micro-controller to RAM through a
serial data interface. It can execute full-screen display
automatically, as well as specific functions such as charac-
ter background, bordering, shadowing, blinking, double
height and width, font by font color control, character but-
ton boxes, frame positioning, frame size control by charac-
ter height and row-to-row spacing, horizontal display
resolution, full-screen erasing, fade-in/fade-out effect, win-
dowing effect, shadowing on window and full-screen self-
test pattern generator.
fonts and 32 multi-color fonts and 2 font sizes, 12x16 or
12x18 for more efficacious applications. The full OSD
menu is formed by 15 rows x 30 columns, which can be
positioned anywhere on the monitor screen by changing
vertical or horizontal delay.
the timing relationship among HFLB, VFLB, and R, G, BIN
with 12-bit resolution at the speed related to the OSD pixel
clock. And the R, G, BIN input level can be programming
by software. MCU can get the measurement data, active
video, front porth and back porth, through I
write operation to keep the appropriate display size and
center.
CWS
LUMAG
PRB
LUMAR
LUMAB
VERTD
VCLKX
DATA
LPN
HORD
BLINK
CWS
DATA
CHS
CH
MTV038 is designed for CRT/LCD monitor applications
MTV038 provides 544 fonts including 512 standard
The auto sizing video measurement module measure
8
8
5
8
CHARACTER ROM
DISPLAY & ROW
WINDOWS &
LUMINANCE &
GENERATOR
CONTROL
ENCODER
POWER ON
REGISTERS
COLOUR
CONTROL
BORDGER
FRAME
RESET
8
LUMA
BORDER
BSEN
SHADOW
OSDENB
HSP
VSP
LUMAR
LUMAG
LUMAB
BLINK
CRADDR
(Revision 1.1)
MTV038
VDD
VSS
VDDA
VSSA
ROUT
GOUT
BOUT
FBKG
HTONE
2
C bus read/
2001/8/21

Related parts for MTV038

MTV038 Summary of contents

Page 1

... No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of the product. Revision 1.1 GENERAL DESCRIPTION MTV038 is designed for CRT/LCD monitor applications to display built-in characters or fonts onto monitor screens. The display operation occurs by transferring data and con- trol information from the micro-controller to RAM through a serial data interface ...

Page 2

... Pixel Clock Input (bit LCD= 1). This is a clock input pin. MTV038 can be driven by an external pixel clock source for all the logics inside. The frequency of XIN must be the integral time of pin HFLB. Bias Resistor (bit LCD= 0). The bias resistor is used to regu- ...

Page 3

... While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV038 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1. ...

Page 4

... C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting from writing the slave address 7AH(write mode), or 7BH(read mode) to MTV038. The protocol is shown in Figure 2. And the auto sizing video measurement data (total 12 bytes) are read only registers and the others are write only registers ...

Page 5

... Input = b7, b6 Initiate 1, X format (a) ROW 1, X format (b) format (c) COL COL -5- MTV038 (Revision 1. Format R1 R0 a,b a a,b a,b a a,b 2001/8/21 ...

Page 6

... Repeat Line # -6- MTV038 (Revision 1. 2001/8/21 17 ...

Page 7

... VCLK Freq = HFLB Freq * HORR * 12 The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input is not present to MTV038, the PLL will generate a specific system clock, approximately 2.5MHz built-in oscillator to ensure data integrity. 3.6 Display & Row control registers The internal RAM contains display and row control registers ...

Page 8

... CWS - Define double width character to the respective row. Revision 1.1 COLUMN # 28 29 COLUMN FRAME CRTL REG COLUMN FRAME CRTL REG CRADDR BOX BGINT FGINT CHS -8- MTV038 (Revision 1. RESERVED 23 31 RESERVED RESERVED b0 LSB b0 CWS 2001/8/21 ...

Page 9

... And only one byte, the attribute byte of button box start character, should be modified when we want to change button box type to raised or depressed button. This is very easy and useful for software programming. Revision 1 BLINK R G -9- MTV038 (Revision 1. 2001/8/21 ...

Page 10

... Character ROM MTV038 character ROM contains 544 built-in characters and symbols including 512 standard fonts and 32 multi-color fonts. The 512 standard fonts are located from address 0 to 511. And the 32 multi-color fonts are located from address 480 to 511 while CFONT bits is set to 1. Each character and symbol consists of 12x18 dots matrix ...

Page 11

... ROW END ADDR LSB MSB WEN LSB -11- MTV038 (Revision 1.1) Magenta Green Blue Cyan b1 b0 LSB b1 b0 WINT WSHD 2001/8/21 ...

Page 12

... The initial value is 40 after power up. Revision 1 LSB VERTD HORD CH4 CH3 CH2 CH1 HORR -12- MTV038 (Revision 1. LSB b0 LSB b0 CH0 b0 LSB 2001/8/21 ...

Page 13

... Vsync leading mismatch with Hsync signal while the bit is set to "1". The initial value is 0 after power up. Revision 1 RSPACE MSB SHADOW FBEN BLEND WENCLR SELVCL/DWE HSP -13- MTV038 (Revision 1.1) b0 LSB RAMCLR FBKGC VSP VCO1/- VCO0/- 2001/8/21 ...

Page 14

... HFLB Freq (KHZ) < 56000/(HORR * 12 56000/(HORR * 12) < HFLB Freq (KHZ) < 112000/(HORR * 12 112000/(HORR * 12) < HFLB Freq (KHZ) < 150000/(HORR * 12 CSR -14- MTV038 (Revision 1.1) 28000/(HORR * 12 CSG CSB 2001/8/21 ...

Page 15

... form the desired video outputs. Revision 1 FSR WW31 WW30 WW21 WW20 ( WH31 WH30 WH21 WH20 ( -15- MTV038 (Revision 1. FSG FSB b1 b0 WW11 WW10 b1 b0 WH11 WH10 2001/8/21 ...

Page 16

... Min. Typ. Max. Unit -16- MTV038 (Revision 1.1) M Pixels N Horizontal lines Note: M and N are defined by the registers of row 15, column 21 and 22 2001/8/21 ...

Page 17

... -> 2.30 +/- 0 -> 2.45 +/- 0 -> 2.60 +/- 0 -> 2.75 +/- 0 -> 2.90 +/- 0 -> 3.00 +/- 0.1 V Revision 1 CFONT3 CFONT2 CFONT1 CFONT0 ID5 ID4 ID3 ID2 -17- MTV038 (Revision 1. ID1 ID0 2001/8/21 ...

Page 18

... The most significant 4 bits of HEND which represents the distance between the last active edge of R,G,BIN input and reference HFLB trailing edge. See Figure 10. Revision 1 HSTART MSB HSTART HEND MSB -18- MTV038 (Revision 1. LSB b1 b0 2001/8/21 ...

Page 19

... R,G,BIN input and reference VFLB leading edge. See Figure 10. Revision 1 HEND HACTIVE MSB HACTIVE HPULSE MSB HPULSE VSTART MSB VSTART -19- MTV038 (Revision 1. LSB LSB LSB LSB 2001/8/21 ...

Page 20

... The least significant 8 bits of VACTIVE which represents the total H line count between two consec- utive VFLB pulses. See Figure 10. Revision 1 VEND MSB VEND OVER VACTIVE MSB VACTIVE -20- MTV038 (Revision 1. LSB LSB 2001/8/21 ...

Page 21

... ABSOLUTE MAXIMUM RATINGS DC Supply Voltage(VDD,VDDA) Voltage with respect to Ground Storage Temperature Ambient Operating Temperature 5.0 OPERATING CONDITIONS DC Supply Voltage(VDD,VDDA) Operating Temperature Revision 1.1 (Revision 1.1) HACTIVE HEND VACTIVE VEND -0 -0.3 to VDD+0 -65 to +150 +70 C +4.75 to +5. +70 C -21- MTV038 2001/8/21 ...

Page 22

... I DOL ( For all OD pins ) Pixel rate=150MHz I load = 0uA Vin = VDD, I load = 0uA Min. Typ 200 100 200 100 500 500 500 500 500 500 -22- MTV038 (Revision 1.1) Min. Max. Units VDD+0.3 V TBD VDD+0.3 V 0.3 * VDD V 0.2 * VDD V TBD 0 0.5 V ...

Page 23

... FIGURE 13. Output and HFLB Timing to Pixel Clock Revision 1.1 t SCKH t SCKL t t DCSU DCH FIGURE 11. Data Interface Timing(SPI) t SCKH t SCKL t t DCSU DCH FIGURE 12. Data Interface Timing(I t pd:: Propagation Delay to R,G,B, FBKG SETUP -23- MTV038 (Revision 1.1) t BCH t HD:STO t SU:STO C) 2 and INT outputs t HOLD 2001/8/21 ...

Page 24

... Max 115 Min 60 +/-5Typ 100Typ 18 +/-2Typ Revision 1.1 312 +/-12 55 +/-20 R40 250 +/-4 7 Typ 35 +/-5 15 Min 60 +/- 5Typ 312 +/-12 250 +/-4 R40 7 Typ 35 +/-5 15 Min -24- MTV038 (Revision 1.1) R10Max ( +/-20 350 +/- +/-4 55 +/-4 310Max R10Max ( +/-20 90 +/-20 350 +/- +/-4 55 +/-4 310Max 2001/8/21 ...

Page 25

... MYSON TECHNOLOGY 9.3 16 Pin SOP 300mil 0.406 +/-0.008 (4x) 0.016 +/-0.004 0.050 9.4 20 Pin SOP 300 mil 0.502+/-0.006inch 20 1 0.016typ. Revision 1.1 0.406 +/-0.013 0.295 +/-0.004 0.015x45 0.098 +/-0.006 0.091 11 0.406+/-0.012inch 0.295+/-0.004inch 0.020x45 10 0.050typ. -25- MTV038 (Revision 1. (4x) 0.028 +0.022 /-0.013 2001/8/21 ...

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