TDC-GPX acam messelectronic gmbh, TDC-GPX Datasheet - Page 3

• Manufacturer Part Number: TDC-GPX
• Description: Precision Time Interval Measurement
• Manufacturer: acam messelectronic gmbh

1. Introduction
1.1 System overview
I-Mode
G-Mode
R-Mode
8 channels with typ. 81 ps resolution
9 LVTTL inputs, optional 3 LVPECL
inputs
5.5 ns pulse-pair resolution with
32-fold multi-hit capability = 182 MHz
peak rate
Trigger to rising or falling edge
Measurement range 9,8 µs endless
measurement range by internal
retrigger of START
10 MHz continuous rate per channel
2 channels with 40 ps resolution
Differential LVPECL inputs, optional LVTTL
Measurement range 0 ns to 65 µs
5.5 ns pulse-pair resolution between edges of
equal slope with 32-fold multi-hit = 182 MHz peak
rate
Minimum pulse width 1.5 ns
Trigger to rising and falling edge
Optional Quiet Mode (no ALU operation and Data-
output during measurements)
20 MHz continuous rate per channel
40 MHz continuous rate per chip
2 channels with 27 ps resolution
Differential LVPECL inputs, optional LVTTL
Measurement range 0 µs up to
5.5 ns pulse-pair resolution with 32-fold multi-hit
capability = 182 MHz peak rate
Trigger to rising or falling edge
Optional Quiet Mode (no ALU operation and Data-
output during measurements)
40 MHz continuous rate per channel
40 MHz continuous rate per chip
0 MHz continuous rate per chip
TQFP100
acam-messelectronic gmbh - Am Hasenbiel 27 - D-76297 Stutensee-Blankenloch - Germany - www.acam.de
TFBGA120
40 µs
IntFlag
ErrFlag
DStart
MTimer
LVPECL inputs
DStop1 DStop2
3
WRN
Configuration
Int and Error
Read/Write logic
0
M-Mode
General
registers
flags
RDN
Logic
Start
2 channels with 10 ps resolution
(70 ps peak-peak)
Differential LVPECL inputs
Measurement range 0 ns up to 10 µs
Single hit per Start and channel
Trigger to rising or falling edge
Quiet Mode (no ALU operation and Data-output
during measurements)
Max. 500 kHz continuous rate per channel
Max. 1 MHz continuous rate per chip
Start retrigger option (besides M-Mode)
Packages: TQFP100, TFBGA120
IO voltage 3.0 V – 3.6 V
Core voltage 2.3 V – 3.6 V regulated by resolution
adjust unit
Data bus: 28 Bit or 2 x 16 Bit asynchronous with
Chipselect, Readstrobe, Writestrobe
40 MHz continuous rate per chip
Address range: 4 Bit
1
CSN
TStart
2
ADR
TStop1
Interface FIFO1
3
OEN/
Reset
Measurement Core
Input Logic
TStop2
Hit FIFOs
4
Data multiplexer
Data bus 28 or 2 x 16
Post-processing
TStop3
5
LVTTL inputs
TStop4
Interface FIFO2
6
TStop5
TDC-GPX
7
EF1
TStop6
8
EF2
TStop7
LF1
Master
reset
TStop8
LF2
PLL
Partial
reset
StartDis
StopDis
40 MHz
ref
Phase
AluTrigger/
Reset
Power-on
reset