ADN2865 Analog Devices, Inc., ADN2865 Datasheet - Page 22

• Manufacturer Part Number: ADN2865
• Description: Continuous Rate 12.3mb/s To 2.7gb/s Clock And Data Recovery Ic W/loop Timed Serdes
• Manufacturer: Analog Devices, Inc.

ADN2865
Information section). Input offset is factory trimmed to achieve
better than 6 mV typical sensitivity with minimal drift. The
limiting amplifier can be driven differentially or single-ended.
SLICE AND SAMPLE PHASE ADJUST (ADN2817
ONLY)
The quantizer slicing level can be offset by ±100 mV to mitigate
the effect of amplified spontaneous emission (ASE) noise or
duty cycle distortion by applying a differential voltage input of
up to ±0.95 V to SLICEP/N inputs. If no adjustment of the slice
level is needed, SLICEP/N should be tied to VEE. The gain of
the slice adjustment is ~0.1 V/V.
If the user is not using the BER monitoring function, sample
phase adjustment can be utilized to optimize the horizontal
sampling point of the incoming data eye. The ADN2865
automatically centers the sampling point to the best of its ability.
However, sample phase adjustment could be used to
compensate for any static phase offset of the CDR and duty
cycle distortion of the incoming eye. Sample phase adjustment
is applied to the incoming eye via the PHASE register. It is
important to note that sample phase adjustment can not be used
if the user is utilising the BER monitoring capability. This is
because the BER monitoring circuit requires control of the
sample phase adjustment circuitry. Also, using the sample phase
adjustment capability uses an additional 180mW of power.
LOSS OF SIGNAL (LOS) DETECTOR
The receiver front end LOS detector circuit detects when the
input signal level has fallen below a user-adjustable threshold.
The threshold is set with a single external resistor from Pin 9,
THRADJ, to VEE. The LOS comparator trip point-versus-
resistor value is illustrated in Figure 2. If the input level to the
ADN2865 drops below the programmed LOS threshold, the
output of the LOS detector, LOS Pin 1, is asserted to a Logic 1.
The LOS detector’s response time is ~500 ns by design, but is
dominated by the RC time constant in ac-coupled applications.
The LOS pin defaults to active high. However, by setting Bit
CTRLC[2] to 1, the LOS pin is configured as active low.
There is typically 6 dB of electrical hysteresis designed into the
LOS detector to prevent chatter on the LOS pin. This means
that, if the input level drops below the programmed LOS
threshold causing the LOS pin to assert, the LOS pin is not de-
asserted until the input level has increased to 6 dB (2×) above
the LOS threshold (see Figure ).
Rev. PrA | Page 22 of 33
The LOS detector and the SLICE level adjust can be used
simultaneously on the ADN2865. This means that any offset
added to the input signal by the SLICE adjust pins does not
affect the LOS detector’s measurement of the absolute input
level.
I
The ADN2865 supports a 2-wire, I
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The 7-bit slave address is factory programmed
to binary ‘1100000’ . The LSB of the word sets either a read or
write operation (see Figure ). Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, defined by a high to low transition on
SDA while SCK remains high. This indicates that an
address/data stream follows. All peripherals respond to the start
condition and shift the next eight bits (the 7-bit address and the
R/W bit). The bits are transferred from MSB to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. This is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCK lines
waiting for the start condition and correct transmitted address.
The R/W bit determines the direction of the data. Logic 0 on
the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first
byte means that the master reads information from the
peripheral.
The ADN2865 acts as a standard slave device on the bus. The
data on the SDA pin is 8 bits long supporting the 7-bit addresses
plus the R/W bit. The ADN2865 has 8 subaddresses to enable
the user-accessible internal registers (see Table 6 through Table
15). It, therefore, interprets the first byte as the device address
and the second byte as the starting subaddress. Autoincrement
mode is supported, allowing data to be read from or written to
2
C INTERFACE
Figure 23. ADN2817 LOS Detector Hysteresis
Preliminary Technical Data
LOS OUTPUT
2
C compatible, serial bus
HYSTERESIS
LOS THRESHOLD
INPUT LEVEL
t