ADN2865 Analog Devices, Inc., ADN2865 Datasheet - Page 13

• Manufacturer Part Number: ADN2865
• Description: Continuous Rate 12.3mb/s To 2.7gb/s Clock And Data Recovery Ic W/loop Timed Serdes
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 6. Internal Register Map
CODE_LSB
1
Table 7. Miscellaneous Register, MISC
D7
x
FDDI_MO
LO_CODE
CTRLA_R
SEL_MOD
HI_CODE
Reg Name
CTRLB_R
All writeable registers default to 0x00.
CTRLA
CTRLC
CTRLD
FREQ0
FREQ1
FREQ2
CTRLB
CTRLE
RATE
MISC
DE
D
D
E
D6
x
LOS Status
D5
0 = No loss of signal
1 = Loss of signal
R/W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
ADDRES
0x0D
0x11
0x22
0x27
0x34
0x35
0x36
0x39
0x0
0x1
0x2
0x3
0x4
0x8
0x5
0x9
0x6
S
1
CDR Bypass
HI_CODE[8]
LO_CODE[8]
Config LOL
FDDI Mode
COARSE_RD[8]
Enable
Static LOL
D4
0 = Waiting for next LOL
1 = Static LOL until reset
MSB
MSB
D7
X
0
0
0
0
Fref Range
RXCLK Alignment
MISC[4]
Drivers
Power
Down
LVDS
Reset
MSB
D6
X
0
0
0
Down CML
Rev. PrA | Page 13 of 33
Acq Mode
Los Status
Threshold
Set Signal
Degrade
Drivers
System
Power
Reset
D5
LOL Status
D3
0 = Locked
1 = Acquiring
0
Subharmonic Ratio
Data Rate/DIV FREF Ratio
Cont Rate /
Single Rate
Static LOL
Degrade
Coarse Data Readback
Squelch
Output
Buffers
Enable
Signal
Align
D4
0
0
Readback CTRLA
Readback CTRLB
Datarate Measurement
Complete
D2
0 = Measuring datarate
1 = Measurement complete
Initiate PBS
LOL Status
LOS forces
acquisition
TX Mode
Sequence
MISC[2]
Datarate
Range
Reset
D3
0
Config LOS
Reverse RX
Holdover
complete
Mode 2A
Datarate
meas
CLK
Bus
D2
0
0
HI_CODE[0]
PRBS Mode[2:0]
Reverse TX
D1
x
Data Rate
Holdover
Mode 2B
Measure
Squelch
Mode
CLK
Bus
D1
X
0
0
Coarse Rate
Readback LSB
D0
COARSE_RD[0]
COARSE_RD[1]
ADN2865
LO_CODE[1]
HI_CODE[1]
COARSE_RD[
LO_CODE[0]
Boost Output
Reference
Lock to
0] LSB
LSB
LSB
LSB
D0
0
0
0
0