ADN2865 Analog Devices, Inc., ADN2865 Datasheet - Page 21

• Manufacturer Part Number: ADN2865
• Description: Continuous Rate 12.3mb/s To 2.7gb/s Clock And Data Recovery Ic W/loop Timed Serdes
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
within 250 ppm of the data frequency. This enables the D/PLL,
which pulls the VCO frequency in the remaining amount and
also acquires phase lock. Once locked, if the input frequency
error exceeds 1000 ppm (0.1%), the loss of lock signal is re-
asserted and control returns to the frequency loop, which
begins a new frequency acquisition starting at the lowest point
in the VCO operating range, 12.3 MHz. The LOL pin remains
asserted until the VCO locks onto a valid input data stream to
within 250 ppm frequency error. This hysteresis is shown in
Figure 22.
LOL Detector Operation Using a Reference Clock
In this mode, a reference clock is used as an acquisition aid to
lock the ADN2865 VCO. Lock to reference mode is enabled by
setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits in order to set the reference
frequency range and the divide ratio of the data rate with
respect to the reference frequency. For more details, see the
Reference Clock (Optional) section. In this mode, the lock
detector monitors the difference in frequency between the
divided down VCO and the divided down reference clock. The
loss of lock signal, which appears on the LOL Pin 30, is de-
asserted when the VCO is within 250 ppm of the desired
frequency. This enables the D/PLL, which pulls the VCO
frequency in the remaining amount with respect to the input
data and also acquires phase lock. Once locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss of lock signal
is re-asserted and control returns to the frequency loop, which
re-acquires with respect to the reference clock. The LOL pin
remains asserted until the VCO frequency is within 250 ppm of
the desired frequency. This hysteresis is shown in Figure 22.
Static LOL Mode
The ADN2865 implements a static LOL feature, which indicates
if a loss of lock condition has ever occurred and remains
asserted, even if the ADN2865 regains lock, until the static LOL
bit is manually reset. The I
LOL bit. If there is ever an occurrence of a loss of lock
condition, this bit is internally asserted to logic high. The
MISC[4] bit remains high even after the ADN2865 has re-
acquired lock to a new data rate. This bit can be reset by writing
a 1 followed by 0 to I
MISC[4] bit remains de-asserted until another loss of lock
condition occurs.
–1000
Figure 22. Transfer Function of LOL
–250
2
C Register Bit CTRLB[6]. Once reset, the
1
2
C register bit, MISC[4], is the static
0
LOL
250
1000
f
(ppm)
VCO
ERROR
Rev. PrA | Page 21 of 33
Writing a 1 to I
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the
functionality described in the previous paragraph. The
CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates
in the normal operating mode, that is, it is asserted only when
the ADN2865 is in acquisition mode and de-asserts when the
ADN2865 has re-acquired lock.
HARMONIC DETECTOR
The ADN2865 provides a harmonic detector, which detects
whether or not the input data has changed to a lower harmonic
of the data rate that the VCO is currently locked onto. For
example, if the input data instantaneously changes from OC-48,
2.488 Gb/s, to an OC-12, 622.080 Mb/s bit stream, this could be
perceived as a valid OC-48 bit stream, because the OC-12 data
pattern is exactly 4× slower than the OC-48 pattern. So, if the
change in data rate is instantaneous, a 101 pattern at OC-12
would be perceived by the ADN2865 as a 111100001111 pattern
at OC-48. If the change to a lower harmonic is instantaneous, a
typical CDR could remain locked at the higher data rate.
The ADN2865 implements a harmonic detector that automati-
cally identifies whether or not the input data has switched to a
lower harmonic of the data rate that the VCO is currently
locked onto. When a harmonic is identified, the LOL pin is
asserted and a new frequency acquisition is initiated. The
ADN2865 automatically locks onto the new data rate, and the
LOL pin is de-asserted.
However, the harmonic detector does not detect higher
harmonics of the data rate. If the input data rate switches to a
higher harmonic of the data rate the VCO is currently locked
onto, the VCO loses lock, the LOL pin is asserted, and a new
frequency acquisition is initiated. The ADN2865 automatically
locks onto the new data rate.
The time to detect lock to harmonic is
where:
1/T
switched from OC-48 to OC-12, then T
ρ is the data transition density. Most coding schemes seek to
ensure that ρ = 0.5, for example, PRBS, 8B/10B.
When the ADN2865 is placed in lock to reference mode, the
harmonic detector is disabled.
LIMITING AMPLIFIER
The limiting amplifier on the ADN2865 has differential inputs
(PIN/NIN), which are internally terminated with 50 Ω to an
on-chip voltage reference (VREF = 2.5 V typically). The inputs
are typically ac-coupled externally, although dc coupling is
possible as long as the input common mode voltage remains
above 2.5 V (see Figure , Figure , and Figure in the Applications
d
16,384 × (T
is the new data rate. For example, if the data rate is
2
C Register Bit CTRLB[7] causes the LOL pin,
d
/ρ)
d
= 1/622 MHz.
ADN2865