HMP41GF7MMP8C Hynix Semiconductor, HMP41GF7MMP8C Datasheet - Page 7

• Manufacturer Part Number: HMP41GF7MMP8C
• Description: 240pin Fully Buffered Ddr2 Sdram Dimms
• Manufacturer: Hynix Semiconductor

Rev 0.1 / May 2008
Advanced Memory Buffer Pin Description
Note:
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/ CK frequency.
2. TESTLO_AB20 and TESTLO_AC20 should be configured for debug purposes on protype DIMMs : each pin should
have a zero ohm resistor pulldown to ground, and an unpoplated resistor pullup to VCC.
These resistors can be replaced on production DIMMs with a direct connection to ground.
SCL
SDA
SA{2:0]
PLLTSTO
VCCAPLL
VSSAPLL
TEST_pin#
TESTLO_pin#
BFUNC
RESET
NC
RFU
V
V
V
V
V
CC
CCFBD
DD
DDSPD
SS
Pin Namel
Serial Presence Detect (SPD) Clock Input
SPD Data Input / Output
PLL Clock Observability Output
Leave floating on the DIMM
Tie to ground on the DIMM
Tie to ground to set functionality as “buffer on DIMM.”
AMB reset signal
No connect. Many NC are connected to VDD on the DIMM, to lower the
impedance of the VDD power islands.
Reserved for Future Use
AMB Core Power(1.5 Volt)
AMB Channel I/O Power(1.5 Volt)
AMB DRAM I/O Power (1.8 Volt)
SPD Power (3.3 Volt)
Ground
SPD Address Inputs, also used to select the DIMM number in the AMB
Analog VCC for the PLL. Tied with low pass filter to VCC.
Analog VSS for the PLL. Tied to
SPD Bus Interface Signals
Power/Ground Signals
Miscellaneous Signals
2
1
240pin Fully Buffered DDR2 SDRAM DIMMs
Pin Description
Total
Count
163
213
655
129
156
18
24
24
5
1
1
3
1
1
1
6
5
1
1
8
1
7