HMP41GF7MMP8C Hynix Semiconductor, HMP41GF7MMP8C Datasheet - Page 12

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HMP41GF7MMP8C

Manufacturer Part Number
HMP41GF7MMP8C
Description
240pin Fully Buffered Ddr2 Sdram Dimms
Manufacturer
Hynix Semiconductor
Datasheet
Rev 0.1 / May 2008
3. Advanced Memory Buffer Block Diagram
Reset#
SMbus
1x2
Northbound
DataOut
Controller
North
Controller
Control
SMbus
LAI
Reset
Thermal
Sensor
Core Control
PLL
& CSRs
Advanced Memory Buffer Block Diagram
CRC Check
Decoder &
Command
Data CRC Gen
& Read FIFO
10x2
I0*12
Failover
36 Deep
Failover
Demux
Write
PISO
FIFO
MUX
Data
Data Merge
14x2
14*6*2
Control & CSRs
Link init SM &
IBIST - TX
Pattern Generator
Re-synch
Re-Time
External MEMBIST
DDR Calibration &
DDR IOBIST/DFX
Sync & Idle
IBIST - RX
1
LAI Logic
Control & CSRs
240pin Fully Buffered DDR2 SDRAM DIMMs
Link init SM &
DRAM Command
Re-synch
Re-Time
IBISt - RX
10x2
I0*12
Data Merge
patterns
DDR State
Controller
Init
& CSRs
Demux
NB LAI
PISO
Buffer
MUX
IBIST - RX
14*12
14x2
Data In
Data
Data
Out
Out
Southbound
DataIn
DDR
IO’s
South
DRAMclock#
DRAM Address
/CommandCopy1
DRAMclock
DRAM Address
/CommandCopy2
DRAM Address
Data/Strobe
12

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