HMP41GF7MMP8C Hynix Semiconductor, HMP41GF7MMP8C Datasheet - Page 19

• Manufacturer Part Number: HMP41GF7MMP8C
• Description: 240pin Fully Buffered Ddr2 Sdram Dimms
• Manufacturer: Hynix Semiconductor

Rev 0.1 / May 2008
IDD Power Supply Currents Specifications.
SAC Timing Parameters by Speed Grade
Note :
1) Assue that Primary channel Drive strength at 100% with De-emphasis at -6.5dBSecondary channel drive strength at
60% with De-emphasis at -3dB when enabled.Address and Data fields are pseudo-random, which provides a 50% tog-
gle rate on DRAM data lines and link lanes when data is being transferred.
Assuming 1 activate command and 1 read/write command per BL=4 transferBL=4.10 lanes southbound and 14 lanes
northbound are enabled and active (12 lanes NB if non-ECC DIMM).
SPD specific assumption:Number of devices on the specific DIMM assumed.Termination of command, address, and
control is actual value used on the DIMM.ECC or non-ECC as per the specific DIMM.
SPD specifies Delta TAMB power spec specific assumptions:Dual rank x8 ECC DIMM assumed (18 DRAM devices
present on DIMM)Modeled with 27 ohm termination for command, address, and clocks, and 47 ohm termination for
control.
ECC DIMM assumed (72 bit data, 14 lanes northbound).AMB specification specifies current for each rail.
Active_1 Total Power
Active_2 Total Power
Idd_Active_1 @1.8V
Idd_Active_2 @1.8V
Training Total Power
Icc_Active_1 @1.5V
Icc_Active_2 @1.5V
Idd_Training @1.8V
Icc_Training @1.5V
Idle_0 Total Power
Idle_1 Total Power
Idle_2 Total Power
Idd_Idle_0 @1.8V
Idd_Idle_1 @1.8V
Idd_Idle_2 @1.8V
Icc_Idle_0 @1.5V
Icc_Idle_1 @1.5V
Icc_Idle_2 @1.5V
Power Supply
L0s Total Power
Idd_L0s @1.8V
Icc_L0s @1.5V
1
240pin Fully Buffered DDR2 SDRAM DIMMs
Max.
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Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
W
W
W
W
W
W
W
Note1)
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