HMP8116 Intersil Corporation, HMP8116 Datasheet - Page 26

• Manufacturer Part Number: HMP8116
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

NO.
BIT
1-0
7
6
5
4
3
2
Aspect Ratio
Mode
Freeze Output
Timing Enable
DVALID Duty Cycle
Control
(DVLD_DCYC)
DVALID Line Timing
Control
(DVLD_LTC)
Missing HSYNC
Detect Select
Missing VSYNC
Detect Select
CLK2 Frequency
FUNCTION
0 = Rectangular (BT.601) pixels
1 = Square pixels
Setting this bit to a “1” freezes the output timing at the end of the field. Resetting this bit
to a “0” resumes normal operation at the start of the next field.
0 = Normal operation
1 = Freeze output timing
This bit is ignored during the 8-bit YCbCr and BT.656 output modes.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
0 = DVALID has 50/50 duty cycle at the pixel output datarate
1 = DVALID goes active based on linelock. This will cause DVALID to not have a 50/50
duty cycle. This bit is intended to be used in maintaining backward compatibilty with the
HMP8112A DVALID output timing.
During 16-bit YCbCr, 15-bit RGB, or 16-bit RGB output modes, this bit is defined as:
During the 8-bit YCbCr and BT.656 output modes, this bit defines the DVALID output sig-
nal as:
This bit specifies the number of missing horizontal sync pulses before the device goes into
the horizontal lock acquisition mode. In mode “0”, the default value of the HPLL Adjust
register should be used. In mode “1”, the typical values the HPLL Adjust register should
be 10
0 = 12 pulses
1 = 1 pulse
This bit specifies the number of missing vertical sync pulses before the device goes into
the vertical lock acquisition mode.
0 = 3 pulses
1 = 1 pulse
This bit indicates the frequency of the CLK2 input clock.
00 = 24.54MHz
01 = 27.0MHz
10 = 29.5MHz
11 = Reserved
0 = DVALID present only during active video time on active scan lines
1 = DVALID present the entire scan line time on all scan lines
0 = Normal timing
1 = DVALID signal ANDed with CLK2
H
to 20
TABLE 14. GENLOCK CONTROL REGISTER
H
.
SUB ADDRESS = 04
HMP8116
26
DESCRIPTION
H
RESET
STATE
01
0
0
0
0
0
0
B
B
B
B
B
B
B