HMP8116 Intersil Corporation, HMP8116 Datasheet - Page 11

• Manufacturer Part Number: HMP8116
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

NOTE:
NOTE:
PIXEL OUTPUT PORT
Pixel data is output via the P0-P15 pins. Refer to Table 3 for
the output pin definition as a function of the output mode.
8-BIT YCbCr OUTPUT
The DVALID output pin may be configured to operate in one
of two ways. The configuration is determined by the
DVLD_LTC bit (bit 4) of the GENLOCK CONTROL register
04
If DVLD_LTC=0, the DVALID output is continuously asserted
during the entire active video time on active scan lines if CLK2
is exactly 2x the desired output sample rate. DVALID being
7. The line numbering for PAL (M) followings NTSC (M) line count minus 3 per the video standards.
8. Definitions in brackets are port definitions during raw VBI data transfers. Refer to the section on teletext for more information on raw VBI.
H
PIN NAME
.
P10
P11
P12
P13
P14
P15
LINES/FRAME
(NTSC, PAL M)
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
480 ACTIVE
8-BIT, 4:2:2, YCbCr
Y0, Cb0, Cr0 [D0]
Y1, Cb1, Cr1 [D1]
Y2, Cb2, Cr2 [D2]
Y3, Cb3, Cr3 [D3]
Y4, Cb4, Cr4 [D4]
Y5, Cb5, Cr5 [D5]
Y6, Cb6, Cr6 [D6]
Y7, Cb7, Cr7 [D7]
LINES 1 - 22 NOT ACTIVE
LINES 263 - 284 NOT ACTIVE
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
240 ACTIVE LINES
240 ACTIVE LINES
(LINES 285 - 524)
(LINES 23-262)
ACTIVE PIXELS
TOTAL PIXELS
PER FIELD
PER FIELD
NTSC M
NOT ACTIVE
LINE 525
FIGURE 8. TYPICAL ACTIVE VIDEO REGIONS
16-BIT, 4:2:2, YCbCr
Cb0, Cr0 [D0
Cb1, Cr1 [D1
Cb2, Cr2 [D2
Cb3, Cr3 [D3
Cb4, Cr4 [D4
Cb5, Cr5 [D5
Cb6, Cr6 [D6
Cb7, Cr7 [D7
TABLE 3. PIXEL OUTPUT FORMATS
Y0 [D0
Y1 [D1
Y2 [D2
Y3 [D3
Y4 [D4
Y5 [D5
Y6 [D6
Y7 [D7
858
720
NTSC
FRONT
PORCH
RECTANGULAR (SQUARE)
n
n
n
n
n
n
n
n
(780)
(640)
]
]
]
]
]
]
]
]
VERTICAL
BLANKING
n+1
n+1
n+1
n+1
n+1
n+1
n+1
n+1
HMP8116
NUMBER OF PIXELS
]
]
]
]
]
]
]
]
ODD FIELD
EVEN FIELD
11
asserted indicates valid pixel data is present on the P15-P8
pixel outputs. DVALID is never asserted during the blanking
intervals. Refer to Figure 9.
If DLVD_LTC=1, DVALID has the same internal timing as the
first mode, but is ANDed with the CLK2 signal, and the result
is output onto the DVALID pin. This results in a gated CLK2
signal being output during the active video time on active
scan lines. Refer to Figure 10.
If 8-bit YCbCr data is generated, it is output following each
rising edge of CLK2. The YCbCr data is multiplexed as [Cb Y
Cr Y Cb Y Cr Y ...], with the first active data each scan line
containing Cb data. The pixel output timing is shown in Fig-
15-BIT, RGB, (5,5,5)
SYNC AND
G0 [D5
G1 [D6
G2 [D7
B0 [D0
B1 [D1
B2 [D2
B3 [D3
B4 [D4
864
720
G3 [D0
G4 [D1
R0 [D2
R1 [D3
R2 [D4
R3 [D5
R4 [D6
PORCH
0 [D7
BACK
PAL
(944)
(768)
n+1
n+1
n+1
n+1
n+1
n+1
n+1
n+1
n
n
n
n
n
n
n
n
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
]
LINES 1 - 22 NOT ACTIVE
LINES 311 - 335 NOT ACTIVE
PAL B, D, G, H, I, N, N
288 ACTIVE LINES
288 ACTIVE LINES
(LINES 336 - 623)
16-BIT, RGB, (5,6,5)
(LINES 23 - 310)
ACTIVE PIXELS
TOTAL PIXELS
PER FIELD
PER FIELD
G0 [D5
G1 [D6
G2 [D7
B0 [D0
B1 [D1
B2 [D2
B3 [D3
B4 [D4
LINES 624-625
G3 [D0
G4 [D1
G5 [D2
R0 [D3
R1 [D4
R2 [D5
R3 [D6
R4 [D7
NOT ACTIVE
n+1
n+1
n+1
n+1
n+1
n+1
n+1
n+1
n
n
n
n
n
n
n
n
]
]
]
]
]
]
]
]
]
]
]
]
]
C
]
]
]
LINES/FRAME
[D0 - D7, where
P8 corresponds
Ancillary Data,
576 ACTIVE
SAV and EAV
YCbCr Data,
Sequences
(PAL)
BT.656
to D0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]
0 [0]