HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 36

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

Pin Description
NTSC/PAL 1
NTSC/PAL 2
NTSC/PAL 3
VBIVALID
INTREQ
HSYNC
P0-P15
VSYNC
DVALID
RESET
BLANK
NAME
FIELD
CLK2
WPE
SDA
SCL
PIN
(Y)
47-51, 54-58,
42, 43, 45,
NUMBER
60, 63, 64
38, 13
PIN
71
70
67
65
66
34
40
41
27
61
44
7
6
5
OUTPUT
INPUT/
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Pixel output pins. See Table 3.
Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The
polarity of HSYNC is programmable. This pin is three-stated after a RESET or soft-
ware reset and should be pulled high through a 10K resistor.
Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polar-
ity of VSYNC is programmable. This pin is three-stated after a RESET or software re-
set and should be pulled high through a 10K resistor.
FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10K resistor.
Composite blanking output. BLANK is asserted during the horizontal and vertical
blanking intervals. The polarity of is programmable. This pin is three-stated after a
RESET or software reset and should be pulled high through a 10K resistor.
Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel da-
ta. This pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
2x pixel clock inputs. All CLK2 pins must be connected together. This clock must be
a continuous, free-running clock.
Reset control input. A logical zero for a minimum of four CLK2 cycles resets the de-
vice. RESET must be a logical one for normal operation.
I
I
White Peak Enable. When enabled (“1”), the video gain is reduced when the A/D out-
put code exceeds 248. When disabled (“0”), the video amplifier will clip when the A/D
output code reaches code 255.
Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that
contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Tele-
text, and Wide Screen Signalling data. The polarity of VBIVALID is programmable.
This pin is three-stated after a RESET or software reset and should be pulled high
through a 10K resistor.
Interrupt Request Output. This is an open-drain output and requires an external 10K
pull-up resistor to V
Composite Video Input. This input must be AC-coupled to the video signal (using a
1 F capacitor) and terminated with a 75 resistor, as shown in the Applications sec-
tion. These components should be as close to this pin as possible for best perfor-
mance. If not used, this pin should be connected to AGND through a 0.1 F capacitor.
Composite Video Input. This input must be AC-coupled to the video signal (using a
1 F capacitor) and terminated with a 75 resistor, as shown in the Applications sec-
tion. These components should be as close to this pin as possible for best perfor-
mance. If not used, this pin should be connected to AGND through a 0.1 F capacitor.
Composite video or Luminance (Y) video input. This input must be AC-coupled to the
video signal (using a 1 F capacitor) and terminated with a 75 resistor, as shown in
the Applications section. These components should be as close to this pin as possi-
ble for best performance. If not used, this pin should be connected to AGND through
a 0.1 F capacitor.
2
2
C interface data input/output.
C interface clock input.
HMP8115
36
CC
.
DESCRIPTION