HMP8115 Intersil Corporation, HMP8115 Datasheet - Page 21

• Manufacturer Part Number: HMP8115
• Description: Ntsc/pal Video Decoder
• Manufacturer: Intersil Corporation

Host Interface
All internal registers may be written to or read by the host
processor at any time, except for those bits identified as
read-only. The bit descriptions of the control registers are
listed in Tables 9-48.
The HMP8115 supports the fast-mode (up to 400 kbps) I
interface consisting of the SDA and SCL pins. The device
acts as a slave for receiving and transmitting data over the
serial interface. When the interface is not active, SCL and
SDA must be pulled high using external 4k
tors. The slave address for the HMP8115 is 88
Data is placed on the SDA line when the SCL line is low and
held stable when the SCL line is pulled high. Changing the
state of the SDA line while SCL is high will be interpreted as
either an I
Figure 20.
DATA WRITE
DATA READ
SDA
SCL
SDA
S
S
SCL
2
C bus START or STOP condition as indicated by
1000 1000 (R/W)
CHIP ADDR
CHIP ADDR
1000 1000
0x88
0x88
CONDITION
START
t
S
BUF
A
A
SUB ADDR
SUB ADDR
ADDRESS
t
LOW
t
SU:DATA
1-7
FIGURE 21. REGISTER WRITE/READ FLOW
t
t
HD:DATA
HIGH
A
A
FIGURE 20. I
REGISTER
POINTED
TO BY
SUB ADDR
FIGURE 19. I
S
H
pull-up resis-
DATA
.
R/W
CHIP ADDR
8
t
R
0x89
HMP8115
A
2
MAY BE REPEATED
OPTIONAL FRAME
2
C SERIAL DATA FLOW
t
2
F
C
C TIMING DIAGRAM
ACK
21
9
DATA
n TIMES
A
During I
address is treated as the control register sub address and is
written into the internal address register. Any remaining data
bytes sent during an I
registers, beginning with the register specified by the
address register as given in the first byte. The address regis-
ter is then autoincremented after each additional data byte
sent on the I
bits within registers or reserved registers are ignored.
In order to perform a read from a specific control register
within the HMP8115, an I
formed to properly setup the address register. Then an I
bus read can be performed to read from the desired control
register(s). As a result of needing the write cycle for a read
cycle there are actually two START conditions as shown in
Figure 21. The address register is then autoincremented
after each byte read during the I
registers return a value of
REGISTER
POINTED
TO BY
SUB ADDR
DATA
A
2
1-7
P
C write cycles, the first data byte after the slave
DATA
2
A
MAY BE REPEATED
C bus during a write cycle. Writes to reserved
OPTIONAL FRAME
DATA
n TIMES
FROM MASTER
FROM HMP8115
2
8
C write cycle are written to the control
00
NA
2
C bus write must first be per-
H
.
ACK
P
9
2
C read cycle. Reserved
S = START CYCLE
P = STOP CYCLE
A = ACKNOWLEDGE
NA = NO ACKNOWLEDGE
CONDITION
STOP
P
t
SU:STOP
2
C