STW4811M STMicroelectronics, STW4811M Datasheet
STW4811M
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STW4811M Summary of contents
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... It supplies the multimedia processor including its memories and peripherals. STw4811 supports the main mass memory standard cards. TM SDIO multimedia peripherals like cameras. Rev 1 STw4811M STw4811N Preliminary Data STw4811 TFBGA 84 6x6x1.2mm 0.5mm pitch STw4811 VFBGA 84 4 ...
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... Clock switching and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Bandgap, biasing and references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VCORE regulator: DC/DC STEP- DOWN regulator . . . . . . . . . . . . . . . 41 VIO_VMEM regulator: DC/DC step- down regulator . . . . . . . . . . . . . . . 41 VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Power supply domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Modes and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 USB enable control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 SD/MMC/SDIO LDO supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 STw4811M/STw4811N ...
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... STw4811M/STw4811N 4.5.2 5 Electrical and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.1 Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.2 Package dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.4 Digital specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.5 USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.6 SD/MMC/SDIO card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1 Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.2 Application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.1 TFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7.2 VFBGA 84 balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Level shifters ...
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... LDO regulators - VPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 42. LDO regulators - VANA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 43. LDO regulators - VAUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 44. Power supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 45. CMOS input/output static characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 46. CMOS input/output dynamic characteristics: I²C interface . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 47. VIO level: USB and control I/ Table 48. VIO level: MMC interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4/87 STw4811M/STw4811N ...
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... STw4811M/STw4811N Table 49. CMOS input/output static characteristics: VBAT level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 50. CMOS input/output static characteristics VMMC level . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 51. USB OTG transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 52. SD/MMC/SDIO card interface Table 53. Components list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 54. Recommended coils . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 56. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch dimensions . . . . . . . . . . . . . . . . . . 79 Table 57. VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch . . . . . . . . . . . . . . . . . . . . 81 Table 58 ...
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... Thermal threshold temperatures for ‘it_warn’ bit and VDDOK ball . . . . . . . . . . . . . . . . . . . 45 Figure 13. USB OTG transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 14. SD/MMC/SDIO block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 15. Propagation and clock/data skew times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 16. STw4811 application schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 17. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing . . . . . . . . . . . . . . . . . . . . . 80 Figure 18. VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch 0.4 drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 6/87 STw4811M/STw4811N ...
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... Low-drop output regulator for processor analog functions (2 mA) – 1 Low-drop output regulator for auxiliary devices (1.5 V, 1.8 V, 2 150 mA) ● Auxiliary device – STw4811M: Vaux OFF at start up – STw4811N: Vaux ON at start up ● USB OTG module – Full and low speed USB OTG transceiver – ...
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... Overview Figure 1. Typical mobile multimedia system 8/87 STw4811M/STw4811N 1 STw4811 ...
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... STw4811M/STw4811N 2 Functional block diagram Figure 2. STw4811 block diagram ...
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... VBAT_ VMEM ANA VAUX VLX_VIO_ “Reserved” VBAT_ANA VMEM MCDATA31 MCFBCLK PWREN DIR VBAT_ GPO1 SCL MMC SW_ VMMC GPO2 RESET STw4811M/STw4811N VANA VPLL VREF_18 “Reserved” “Reserved” “Reserved” VBAT_ VMINUS_ PON VPLL_ANA VCORE VLX_ VBAT_ VCORE VCORE ID DP “ ...
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... STw4811M/STw4811N Table 2. STw4811 balls function Ball Ball name General supplies D1 VBAT_DIG C3 VMINUS_DIG C6 VBAT_ANA B5 VMINUS_ANA F9 VBAT_USB J9 VMINUS_USB A9 VREF_18 Control balls C8 PON K4 SW_RESETn J2 VDDOK J3 PORn H6 PWREN C1 TCXO_EN B2 REQUEST_MC J6 SCL H7 SDA D2 MASTER_CLK A1 CLK32K_IN K3 CLK32K Ball type VDDD-VBAT Battery supply for digital/oscillator VSSD Ground for digital and oscillator ...
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... DO(VIO_VMEM) Differential receiver output Positive data line in the USB mode, or serial AIO(VUSB) data input in the UART mode Negative data line in the USB mode, or serial AIO(VUSB) data output in the UART mode. ID ball of the USB detector used for protocol AI(VBAT-USB) identification. STw4811M/STw4811N Description ...
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... STw4811M/STw4811N Table 2. STw4811 balls function (continued) Ball Ball name General supplies H10 CP J10 CN G10 VBUS F10 VUSB G9 USBSCL H9 USBSDA H8 USBINTn SD/MMC/SDIO balls G3 MCCMDDIR K2 MCDAT0DIR K9 MCDAT2DIR H4 MCDAT31DIR G2 MCCLK H5 MCFBCLK H1 MCCMD K1 MCDATA0 H2 H3 MCDATA[3: LATCHCLK G1 CLKOUT F2 CMDOUT Ball type C plus flying capacitor AIO(VBUS) (VBUS level 4 ...
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... DIO(VMMC) Bidirectional data0 between STw4811 and card Ω Pull up 1.5M DIO(VMMC) Bidirectional data[3:1] between STw4811 and Ω Pull up 1.5M card. VDDA-VBAT Battery supply for VMMC AIO VMMC supply output AO General purpose output AO General purpose output connected to ground left open STw4811M/STw4811N Description ...
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... STw4811M/STw4811N 4 Functional description 4.1 Introduction The STw4811 integrates all the power supplies for a multimedia processor as well as memories and peripherals: ● Two switched mode power supply regulators: one for the multimedia processor core, one for multimedia processor I/Os and memories ● Three low-drop output regulators for multimedia processor analog supplies (PLL and others) and auxiliary components ● ...
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... SLEEP to high power mode and informs multimedia processor with VDDOK at high level ( Figure 4 ). Note: The default state of VAUX is different for STw4811M and for STw4811N. - VAUX default state is OFF at start up for STw4811M. - VAUX default state start up for STw4811N. VAUX can be programmed in high power mode only by asserted pdn_vaux bit to “1” (Table 18) ...
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... STw4811M/STw4811N Figure 3. Start-up timing OFF VBAT PON ball 300µs PDN__OSC 7.77ms (9.46ms wc) PDN_regulators VDDOK ball (*) CLK32K_IN ball PORn ball PWREN ball Internal_OSC MASTER_CLK ball TCXO_EN ball REQUEST_MC ball Voutput(s) ball CLK32K ball Delays are worst case maximum delays (*) If 32 kHz available before VDDOK signal rising edge, OFF2 state duration is null All regulators are started with PDN_regulators or EN_regulators but can be switched off from the beginning or during application by software, ‘ ...
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... REQUEST_MC output gate between PWREN (coming from multimedia processor) and TCXO_EN (coming from modem supply synchronized on 32 kHz, except during power-up where PWREN is masked and considered as high. REQUEST_MC enabled or disabled the master clock oscillator device. 18/87 Sleep “0” STw4811M/STw4811N HPM ~100µs ...
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... STw4811M/STw4811N 4.2.2 POWER OFF / VDDOK ● In case of VDDOK falling edge due to under voltage on VCORE or VIO_VMEM detection, or ‘it_twarn’ bit set to “1” ( (PORn low during a minimum time of 333 µs) and restarted with no time-out. (see Figure case of VDDOK falling edge because PWREN balls equals “0”, there is no reset (PORn still high). ● ...
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... Then STw4811 sends an acknowledge at the end bit transfer. The next 8 bits correspond to the register address followed by another acknowledge. The 8-bit data field is sent last, followed by a last acknowledge. 20/87 SCL SDA usb_i2c_ctrl Main registers SCL or USBSCL USB registers SDA or USBSDA STw4811M/STw4811N ...
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... STw4811M/STw4811N Table 3. Device AdrID6 AdrID5 AdrID4 Table 4. Register address b7 b6 RegADR7 RegADR6 RegADR5 Table 5. Register data b7 b6 DATA7 DATA6 DATA5 I2C interface modes Figure 7. Control interface: I2C format DEVICE ADDRESS WRITE SINGLE BYTE START DEVICE ADDRESS ...
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... Power control registers ( 1Eh to 1Fh 20h Configuration 2 register ( 21h VCORE_sleep ( 1. Controlled by USB_I2C_CTRL bit of power control register ( 22/87 Comment Table 9 to Table 17 ) Table 18 ) Table 19 Table Table 28 ) Table 29 ) Table 23 ) STw4811M/STw4811N I2C control USBSDA / USBSCL or SDA / SCL SDA / SCL SDA / SCL SDA / SCL SDA/SCL (1) ...
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... STw4811M/STw4811N Register summary Table 7. Register summary Register Addr. 7 00h 1 Vendor ID 01h 0 02h 0 Product ID 03h 0 04h USB control Not used uart_en register 1 05h 06h USB control vbus_ register 2 chrg 07h USB interrupt 08h cr_int source 0Ah USB interrupt cr_int latch 0Bh 0Ch ...
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... USB control register 2 USB control register 2 USB interrupt source Not used USB interrupt latch USB interrupt latch USB interrupt mask false USB interrupt mask false USB interrupt mask true USB interrupt mask true USB_EN Address 00h 01h 02h 03h STw4811M/STw4811N Table 23 ). Type R R R/W R/W R/W R/W R R/W R/W R/W R/W R/W ...
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... STw4811M/STw4811N USB control register 1 Table 11. USB control register 1 (address = 04h set and 05h clearh Not used uart_en - R/W Bits Name 6 uart_en 5 oe_int_en 4 bdis_acon_en 2 dat_se0 1 suspend 0 speed bdis_ oe_int_en not used acon_en R/W R/W - Value Settings 0 Inactive 1 UART logic buffers are enabled 0 Inactive ...
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... Inactive 1 Charge VBUS through a resistor 0 Inactive 1 Discharge VBUS through a resistor to ground. 0 Inactive 1 Provide power to VBUS 0 Inactive 1 Connect ID ball to ground 0 Inactive 1 Connect DN pull-down 0 Inactive 1 Connect DP pull-down 0 Inactive 1 Connect DN pull-up 0 Inactive 1 Connect DP pull-up STw4811M/STw4811N dp_ dn_pullup dp_pullup pulldown R/W R/W R/W Default ...
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... STw4811M/STw4811N USB interrupt source register Table 13. USB Interrupt source register (address = 08h cr_int bdis_acon R R Bits Name 7 cr_int 6 bdis_acon 5 id_float 4 dn_hi 3 id_gnd_forced 2 dp_hi 1 sess_vld vbus_vld 0 USB interrupt source register indicates the current state of the signals that can generate an interrupt. USB latch register Table 14 ...
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... The corresponding bit in the interrupt enable low register is set, and the associated signal changes from high to low The interrupt latch register is cleared by writing “1” to its clear address. 28/ id_float dn_hi R/W R id_float dn_hi R/W R/W STw4811M/STw4811N id_gnd_ dp_hi sess_vld forced R/W R/W R id_gnd_ dp_hi sess_vld vbus_vld forced ...
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... STw4811M/STw4811N USB EN register Table 17. USB EN register (address = 10h B_sess_ Not used end - R Bits Name 1 usb_en 2 th_Bdevice 6 B_sess_end Not used - - - Value Settings 0 Inactive 1 Enable USB PHY 0 Threshold for vbus_valid = 4 Threshold for vbus_valid = 3. Vbus voltage is below B_session_end threshold (0.2 to 0.8 V) ...
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... In STw4811M, pdn_vaux = 0 is the default. In STw4811N, pdn_vaux = 1 is the default. In Flash OTP two registers allow to program STw4811 energy management part. These two registers are at addresses 1E and 1F and must be programmed with 1F register first followed by 1E register. 30/ monitoring_vio_ ...
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... STw4811M/STw4811N Power control register at address 1Eh Table 19. Power control register - General information (Address = 1Eh reg address 3 bits LSB’s R/W Bits Name reg address 3 [7:5] bits data din/ [4:1] dout 4 bits 0 EN Power control register at address 1Fh Table 20. Power control register - General information (Address = 1Fh) ...
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... STw4811M/STw4811N Address 1Eh vcore_sel [3:0] Settings 0 EN Default 0111 ...
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... STw4811M/STw4811N Power control register at address 06h Table 23. Power control register at address 06h Address 1Fh Not used Bits Name vpll_sel[1: 06h and 07h address [3:2] vaux_sel[1:0] 1 usb_i2c_ctrl Power control register at address 07h Table 24. Power control register at address 07h Address 1Fh ...
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... VAUX stays in high power mode 1 VAUX goes in sleep mode When PWREN is low: 0 VIO_VMEM stays in high power mode 1 VIO_VMEM goes in sleep mode When PWREN is low: 0 VCORE stays in high power mode 1 VCORE goes in sleep mode STw4811M/STw4811N Address 1Eh en_ en_clk en_ not mo squarer vana ...
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... STw4811M/STw4811N Power control register at address 0Ah Table 27. Power control register at address 0Ah Address 1Fh Not used Bits Name 4 vaux_force_sleep vio_vmem_force_ 2 sleep 1 vcore_force_sleep Value 0 0: Vaux keeps the state controlled by Vaux_sleep and Pwren 1 1: VAUX goes in sleep mode (for any PWREN level) ...
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... Mask TWARN interruption (it_twarn bit) through VDDOK 0 Internal LDO VMMC is used 1 External VMMC is used 0 Inactive 1 IT_WAKE_UP ball masked 0 GPO1 in High impedance 1 GPO1 at low level 0 GPO2 in High impedance 1 GPO2 at low level 0 Not used 1 STw4811M/STw4811N 2 1 mask_it_ external_ mask_ wake_up vmmc R/W R/W Settings 0 twarn R/W Default ...
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... STw4811M/STw4811N VCORE_sleep register Table 29. VCORE_sleep register (Address = 21h) Register Bit name Type Bits Name [3:0] vcore_sleep[3:0] vcore_available 4 (1) 1. read operation reset the value after status read operation from APE, functionality is described in Section 4.3.7: Power supply monitoring vcore_ available R Value = 1.00V 0000 0001 = 1 ...
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... HPM mode restart the device with the OFF/ON sequence on PON (PON = 1 then 0 then 1) Note: When present the Master clock should remain connected up to sleep mode. 38/87 section), ‘it_warm’ bit of Configuration 1 register is the temperature Table 18 ). STw4811M/STw4811N Table 28 ) ...
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... STw4811M/STw4811N Figure 9. Clock switching between master and internal clock (1) * Phase delay is less than 90 between int and ext clock internal clock PON INT_OSC INT_OSC_OK MASTER_CLK_OK PDN_INT_OSC CONTROL_SWITCH MASTER_DIV_CLK STEP_DOWN_CLK transition external clock Functional description Third rising edge after switching 39/87 ...
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... Bandgap, biasing and references Figure 10. Block diagram of biasing and references of the device BG 40/87 Table and ). In this mode, the regulator is switched off and Table 22 to Table 27 ). Voltage reference control Bias generator STw4811M/STw4811N VREF_18 All internal references All internal biasing ...
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... STw4811M/STw4811N 4.3.2 VCORE regulator: DC/DC STEP- DOWN regulator This regulator drives the core of the multimedia processor. VCORE is a DC/DC step-down regulator that generates the regulated power supply with very high efficiency. The 16 voltage levels enable dynamic voltage and frequency scaling suitable for any supply voltage of CMOS process, they also follow the processor process roadmap ...
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... Sleep mode ) STw4811M/STw4811N section. Table 23 and Table 24 ). Table 23 Table 24 ...
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... STw4811M/STw4811N 4.3.6 VAUX This LDO is dedicated either to the multimedia processor input/output signals or to the auxiliary devices. Power supply values are 1.5, 1.8, 2.5, 2.8 V with 150 mA full load and 0 sleep mode. In case of 1 the output, this LDO can be supplied by using VIO_VMEM DC/DC converter (1.8 V). One pad feed-back is used. ...
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... Table 31. Thermal threshold values Thermal warning threshold Rising threshold Falling threshold Thermal shutdown threshold Threshold 44/87 High power vcore_sel[3:0] - vpll_sel[1:0] - vaux_sel[1:0] vmmc_sel[2:0] Section 4.5 Description STw4811M/STw4811N Supply domains Sleep Power down vcore_sleep[3:0] vcore_sleep en_vcore vcore_force_sleep vio_vmem_sleep vio_vmem_force_sleep - en_vpll - en_vana vaux_sleep pdn_vaux vaux_force_sleep - ...
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... STw4811M/STw4811N Figure 12. Thermal threshold temperatures for ‘it_warn’ bit and VDDOK ball ‘it_warn’ bit VDDOK ball 4.4 USB OTG module This transceiver complies with the USB specification; ● Universal Serial Bus Specification Rev 2.0 ● On the Go supplement to the USB specification Rev 1.0-a ● ...
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... VBUS_MONITOR vbus_vld 4.4 V sess_vld 1.9 V B_sess_end 0.6 V vbus_dischrg RXD DAT_VP Diff Tx SEO_VM OE_TP_INT out_diff_Rx Diff Rx suspend SE_DP VP SE_DN VM id_float sess_vld id_gnd OR ID Detector STw4811M/STw4811N 100 mA RA_BUS_IN vbus_chrg Gnd VUSB_LDO DP_MONITOR 5 cr_int R DP < [0.4 to 0.6] V TRANCEIVER RXD dp_pullup dn_pullup dn_pulldown dp_pulldown VBAT_USB R RID_PU 0.85*ID 4.7 R 0.15*ID id_gnd R ...
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... STw4811M/STw4811N Interrupt management IT_WAKE_UP: with only VBAT supply, no other supply available, when a USB cable is plugged this interrupt is activated to wake up the host or the modem, depends of application (open drain, active low). By default this feature is available independently of PON level, it can be masked when PON = 1 by ‘mask_it_wake_up’ bit of configuration 2 register (see USBINTn: This interrupt ball is dedicated to USB protocol and sent to multimedia processor ...
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... Not used Not used DIFF_RX DIFF_RX DIFF_RX DIFF_RX STw4811M/STw4811N Table 11 ) Table 11 ) Comments Single ended data (zero sent) Single ended data (1 sent) Force single ended zero DAT_VP drives the level of DP SE0_VM drives the level of DN ...
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... STw4811M/STw4811N Table 33. Data transmission via USB control register 1 (DAT_SE0 mode) - Suspend = 1 Inputs USB mode (dat_se0) USBVP 1 (DAT_SE0 mode (DAT_SE0 mode (DAT_SE0 mode (VP_VM mode (VP_VM mode (VP_VM mode (VP_VM mode oe_int_en = 1 and suspend=1 ( USB control register 1 - becomes an output used to generate multimedia processor ...
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... The A-device can disable both pull-down resistors during the interval of a packet transmission when acting as either host or peripheral. When the line is not used, the pull-down is activated and the maximum level on this ball should not exceed 0.342 V. 50/87 STw4811M/STw4811N Table 11 ). Table 12 ) are used to ...
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... STw4811M/STw4811N Data line pull-up resistance The two bits of USB control register dp_pullup and dn_pullup ( connect/disconnect pull-up resistors. Full-speed and low-speed devices are differentiated by the position of the pull-up resistor from the peripheral device. A pull-up resistor is connected to DP line for a full-speed device and a pull-up resistor is connected to DN line for a low-speed device. The pull-up resistor value is in the range of 900 Ω ...
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... If VBUS is “ON” before going to sleep mode, it remains “ON” in sleep mode. LDO USB From VBAT_USB, a LDO provides VUSB supply, ‘usb_en’ bit of USB_EN register ( is used to enable/disable the VUSB LDO and the transceiver. 52/87 Table 12 ); This pull-down is used for Table 13 )) (refer to OTG specifications, Rev 0.92, §2.7, STw4811M/STw4811N Figure 13 ). Table 17 ) ...
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... STw4811M/STw4811N 4.4.3 USB enable control STw4811 OFF In this state: PON ball = 0 In this state, the overall system is able to detect USB connection through IT_WAKE_UP ball and with VBUS session valid comparator and ID detection ON. IT_WAKE_UP ball is activated (low level if tied by an external Pull Up resistor to VIO or VBAT) in either of the two following cases: ● ...
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... LDO. In this configuration, ‘pdn_vmmc’ bit is set to “0”, ‘mmc_ls_status’ is set to “0” ( ‘external_vmmc’ bit is set to “1” ( 54/87 VBAT_VMMC VMMC LDO 150 mA Driver 3*RA RB Table 28 ). STw4811M/STw4811N EMIF CLKOUT SD, MMC SDIO OR RC cards CMDOUT DATAOUT0 DATAOUT[3:1] LATCHCLK ...
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... STw4811M/STw4811N 4.5.2 Level shifters Signal shifting cards voltage level value is automatically done by the multimedia processor system. Following a card detection, the multimedia processor starts the SD/MMC/SDIO application by writing in the configuration 1 register ( output supply and then starts the protocol initialization. The module includes: ● ...
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... The configuration wxx_sleep = 0 (device in active mode) and vxx_force_sleep = 1 (device in sleep mode, but no priority level on this bit) is forbidden. 56/87 Description Human body model Charge device (2) model Description Table 26 Table 27 and . Table 26 STw4811M/STw4811N Values -0 -30 to +85 ( -300 to +1000 Min. Typ. Max Table 27 and ...
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... STw4811M/STw4811N In all the following tables: – “High power mode” is defined as “SLEEP = ‘0’” – “Sleep mode” is defined as “SLEEP = ‘1’” Use Table 27 to refer to each Vxxx supply (VCORE or VIO_VMEM or VAUX). 5.3.1 Operating conditions Table 37. Operating conditions (Temp range: -30 to +85 °C) ...
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... V = 3.6 V BAT I = 200 mA OUT V : [2.7; 4.8]V BAT I : [0.1; 600] mA OUT 0 OUT ‘en_vcore’ Vpp = 0 [0; 20] kHz ΔV = 300 mV BAT µ [1; 600] mA OUT 100 STw4811M/STw4811N Typ. Max. Units 3.6 4 mVpp 1.45 +3.7% 1.40 1.38 1.36 1.34 1.32 1.30 1.28 V 1.26 1.24 1.22 1.20 +4.25% 1.15 1.10 1.05 1.00 +5% 600 1.2 1.4 A ...
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... STw4811M/STw4811N Table 39. VCORE DC/DC step-down converter (continued) Symbol Description VCORE regulator in sleep mode (SLEEP= ‘1’) V Input power supply Battery voltage BAT VCORE output V RIPPLE voltage ripple L Line regulation IR L Load regulation DR VCORE output I OUT current P Power efficiency EFF I Quiescent current Q Transient line ...
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... Including output voltage temperature coefficient, DC line and load regulations, voltage reference accuracy, industrial manufacturing tolerances and ripple voltage due to switching 2. Guaranteed by design 60/87 Test conditions Min. 2 [2.7; 4.8]V BAT I : [0. OUT V = 3.6 V BAT I = [0. OUT OUT ΔV = 300 mV BAT µ STw4811M/STw4811N Typ. Max. Units 3.6 4 mVpp µ ...
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... STw4811M/STw4811N 5.3.5 LDO regulators VPLL Table 41. LDO regulators - VPLL Symbol Description VPLL regulator in high power mode unless otherwise specified, VPLL = 1 Input power supply Battery voltage BAT V Output voltage OUT I Output current OUT Short-circuit I SHORT limitation I Quiescent current Q Power-down I LKG current Power supply ...
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... [0.1; 10] mA OUT µ Test conditions Min 1.5V 1.7 OUT V = 1.8/2.5 V 2.7 OUT OUT ’vaux_sel’[1:0] 00 (default) - 220 OUT STw4811M/STw4811N Typ. Max. Units 3.6 4.8 V 2.5 + µA 1 µ Typ. Max. Units 4.8 V 3.6 4 ...
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... STw4811M/STw4811N Table 43. LDO regulators - VAUX (continued) Symbol Description Power-down I LKG current Power supply (1) PSRR rejection L Line regulation IR (1) L Load regulation DR Transient line L IRT regulation Transient load L DRT regulation t Settling time S VAUX regulator in sleep mode (’pdn_vaux’= 1, SLEEP=’1’) V Input power supply ...
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... V OH voltage 1. Vio is for VIO_VMEM 64/87 Test conditions Min. -3% -3% 2.7 Test conditions Min. 0.7*V IO -1.0 -1.0 IOL = 3mA (with open drain or open collector) IOL = 3mA (with open drain or 0.8*V IO open collector) STw4811M/STw4811N Typ. Max. Units VCORE-150 +3% mV 1.65 +3% V 3.6 4.8 V 100 Typ. Max. Units 0.3 ...
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... STw4811M/STw4811N 5.4.2 CMOS input/output dynamic characteristics: I2C interface Table 46. CMOS input/output dynamic characteristics: I²C interface Symbol I²C interface ( Figure 8 Fscl Clock frequency thigh Clock pulse width high tlow Clock pulse width low tr SDA, SCL, USBSDA, USBSCL rise time 20+0.1*Cb tf SDA, SCL, USBSDA, USBSCL fall time ...
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... Output fall time OF t Output rise time OR C Driving capability I/O 1. Vio for VIO_VMEM 66/87 Test conditions Min. 0.7*Vio -1.0 -1.0 IOL = 4 mA IOL = 4 mA 0.8*Vio Capacitance 10pF Capacitance 10pF STw4811M/STw4811N Typ. Max. Units 0.3*Vio V V 1.5 µA 1.5 µ 0.2*Vio 100 pF ...
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... STw4811M/STw4811N MMC interface Table 48. VIO level: MMC interface Symbol Description MMC interface: MCCLK, MCFBCLK, MCCMDDIR, MCCMD, MCDATA2DIR, MCDAT2, MCDATA0DIR, MCDAT0, MCDAT31DIR, MCDAT3, MCDAT1 Low level input ( voltage High level input V IH voltage Low level input I IL current High level input ...
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... Output rise time OR C Driving capability I/O 68/87 Test conditions Min. PON PON 0.7*Vbat PON -1.0 PON -1.0 IT_WAKE_UP, GPO1, GPO2 IOL = 2 mA IT_WAKE_UP, GPO1, GPO2 0.8*Vbat IOL = 2 mA Capacitance 10pF Capacitance 10pF STw4811M/STw4811N Typ. Max. Units 0.3*Vbat V V 1.5 µA 1.5 µ 0.2*Vbat 100 pF ...
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... STw4811M/STw4811N 5.4.5 CMOS input/output static characteristics: VMMC level Table 50. CMOS input/output static characteristics VMMC level Symbol Description DATAOUT0, DATAOUT1, DATAOUT2, DATAOUT3, CMDOUT, LATCHCLK, CLKOUT Low level input V IL voltage High level input V IH voltage Low level input I IL current High level input ...
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... [50;100] pF LOAD 50 [50;100] pF LOAD 50 USBVP & USBVM : 90 - Trise & Tfall < Skew < 0. 1.3 Battery voltage 3.1 STw4811M/STw4811N Typ. Max. Units 100 ns 100 ns 100 ns 100 111 % 300 ns 300 ns 125 % 2 V 3.6 4 ...
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... STw4811M/STw4811N Table 51. USB OTG transceiver (continued) Symbol Description Threshold VBUS monitoring V VBUS valid Aval V Threshold device th_dev V VBUS session valid Bses V B_session_end Bsess_end VBUS R A_BUS_ IN T A_VBUS_ RISE Data line pull-down resistance R PD_DPDN Data line pull-up resistance R PU_DP R PU_DN PULL-DOWN on VBUS ...
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... OUT VBAT= 3.6V mA. OUT Battery voltage: V min = VUSB+0.1 BAT V + 0.1V OUT V min= BAT 3 0.1V OUT No load +0.2V BAT OUT 45 f < 20 kHz ΔV = 300 mV BAT 10µ STw4811M/STw4811N Typ. Max. Units 3 0.8 V 3.6 4 5.25 V 1 100 3.6 5.5 V 3.1 3.2 V 320 ...
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... STw4811M/STw4811N Table 51. USB OTG transceiver (continued) Symbol Description Settling time t S OFF->ON Discharge time t D ON>OFF 1. From 4 5.5 V, charge pump is “Off” and no OTG feature is provided 2. Guaranteed by design 5.6 SD/MMC/SDIO card interface Table 52. SD/MMC/SDIO card interface Symbol Description VMMC regulator specifications (’pdn_vmmc’ ...
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... To prevent bus from floating With CL = 30pF With CL = 30pF Figure 15 Figure 15 Figure 15 Reference is CLKOUT Figure 15 Reference is MMCLK Bus line capacitance f < 52 MHz Bus line capacitance f < 52 MHz STw4811M/STw4811N Typ. Max. Units 25 mV 100 µ 1.5 MΩ 1.5 MΩ 52 MHz 400 kHz 7 ns ...
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... STw4811M/STw4811N Figure 15. Propagation and clock/data skew times 2 ns MCCLK 90% MCCMD MCDATA[3:0] 10% MCFBCLK T PHC CLKOUT CMDOUT DATAOUT[3:0] LATCHCLK 2 ns CLKOUT 90% CMDOUT DATAOUT[3:0] 10% LATCHCLK T PCH MCCLK MCCMD MCDATA[3:0] MCFBCLK 2 ns 90% 50% 10% t MCCLK 10% 50% MCDATA[3: PHC 2 ns 90% 50% 10% CLKOUT 10% t 50% DATAOUT[3: PCH ...
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... See Table 54 for recommended coils Part number DCR (Ω) 0.28 0.16 0.14 0.15 0.32 0.19 STw4811M/STw4811N Function VIO_VMEM output filter VCORE output filter VBAT_VIOVMEM decoupling VBAT_ANA decoupling VBAT_VCORE decoupling VPLL output filter VANA output filter VREF output filter VUSB output filter VAUX output filter Flying capacitor for charge pump ...
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... STw4811M/STw4811N Table 55. Other ST components Name EMIF02 EMIF06 Order code EMIF02USB05 USB ESD/EMI Protection EMIF06-HMC01F2 MMC Interface ESD/EMI Protection Application information Function 77/87 ...
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... MCDAT[3,1] MCDAT2DIR MCDAT2 GPO1 GPO2 (*) The usefulness of these capacitors depend of PCB layout (**) Master Clock can be conected on this ball. In this case see the feature use restriction in section 4.2.3 78/ STw4811 STw4811M/STw4811N (*) C14 VBAT_VPLL_VANA C6 VPLL C7 VANA C8 VREF (*) C15 VBAT_VAUX C13 VAUX (*) ...
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... STw4811M/STw4811N 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...
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... Figure 17. TFBGA 84 balls 6x6x1.2mm body size / 0.5 ball pitch drawing Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 80/87 STw4811M/STw4811N ...
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... STw4811M/STw4811N 7.2 VFBGA 84 balls See Figure 18: VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch 0.4 drawing Table 57. VFBGA 84 balls / 4.6x4.6x1.0 mm body size / 0.4 mm ball pitch Drawing dimensions (mm ddd eee fff 1. These measurements conform to JEDEC standards Package mechanical data Min. Typ. 0.15 0.19 0.615 ...
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... Figure 18. VFBGA 84 balls 4.6x4.6x1.0 mm ball pitch 0.4 drawing Note: The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. A distinguishing feature is allowable on the bottom surface of the package to identify the terminal A1 corner. Exact shape of each corner is optional. 82/87 STw4811M/STw4811N ...
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... STW4811MBHDT/LF STW4811MBRA/LF STW4811MBRAT/LF STW4811NBHD/LF STW4811NBHDT/LF STW4811NBRA/LF STW4811NBRAT/LF Note: STw4811M: Vaux OFF at start up STw4811N: Vaux ON at start up Package TFBGA84 1 0.5 mm pitch TFBGA84 1 0.5 mm pitch VFBGA 84 - 4.6x 4 0.4 mm pitch VFBGA 84 - 4.6x 4 0.4 mm pitch TFBGA84 1 0.5 mm pitch TFBGA84 1 0.5 mm pitch VFBGA ...
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... Replaced msk_monitor_sleep with ‘not used’ in summary and Table 28: Configuration 2 register (Address = 20h) Removed reference to sleep modes and msk_monitor_sleep bit in 0.6 Section 4.3.7: Power supply monitoring Corrected VOUT typical value at 1111 to be 1.45V in Table 29 . STw4811M/STw4811N Changes Figure 14: and . Table 52: . Section 5.3: Power supply and added the same , ...
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... STw4811M/STw4811N Table 59. Document revision history (continued) Date 23-Jan-2007 27-Mar-2007 18-May-2007 Revision Replaced normal mode with high power mode in the whole document. Figure 3: Start-up timing timing and replaced the text in the note. Register reset - Added some text at the end of the last sentence. ...
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... Revision history Table 59. Document revision history (continued) Date 08-Aug-2007 05-Sep-2007 86/87 Revision Section 4.3.9: Thermal shut-down Updated 0.9 codes Initial release on www.st.com. 1 Reviewed the first sentence in ‘typical’ parameters. STw4811M/STw4811N Changes Table 58: Order and Section 5.3: Power supply to precise ...
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... STw4811M/STw4811N Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...