SSD2119 Crystalfontz America, Inc.,, SSD2119 Datasheet - Page 3

• Manufacturer Part Number: SSD2119
• Description: 320 Rgb X 240 Tft Lcd Driver Integrated Power Circuit, Source And Gate Driver And Ram
• Manufacturer: Crystalfontz America, Inc.,

SSD2119
Version
0.46
0.47
0.48
0.49
0.50
1.0
1.1
Change Items
P. 68-70 Updated all temperature to -40 to 85°C
P.74 Updated Table 15.2 The Function of 6800-series parallel interface
P.52 Updated Internal Oscillator Frequency
P.76 Updated Table 15.4 Mapping for Writing Pixel Data in generic mode
P.79-80 Updated 16.2 Display OFF Sequence and 16.3 Sleep Mode Display Sequence
P.35 Updated Device Code
P.33 Remove SR(status read) register
P.87 Added Section 21 OTP explanation
P.53 Added OTP sequence step 4 “Turn on the display as normal to 65k/262k color mode”
P.34, 56 Updated GDDRAM X Y address
P52. Add Deep sleep mode command R12 and correct R10 description
P37. Add R12.
P.50 Corrected
Dmode=1 : Display engine will be clocked by DOTCLK pin and onchip oscillator will be off
(POR, if PS:00xx)
Dmode=0 : Display engine will be clocked by on chip oscillator and ignore DOTCLK pin
P.71 Corrected Table 13-2: RGB Timing Characteristics
Dotclock period to ns
P.48 Swapped R12 and R10 in deep sleep sequence
P.80, 82 Added Halt, Deep sleep sequence.
P.67 Updated power consumption information of sleep mode
P.67 Added power consumption information of Halt and Deep sleep mode
P.67 Added “The leakage current is below 100uA if Reset keeps at low state when power on”
P.67 Updated deep sleep mode max current to 15uA
P.26 RESB pin description amend to “An external reset pulse to RESB is required for power
up (sequence).” This change is to prevent unexpected internal RESET by excessive electrical
stress.
P.52 Corrected R1EH VCM default to x2B
P.53 Added analogue setting register description
P.48-49 Added VSH[2:0] and HVCI of R12h
P.68-69 Change read cycle to 450ns
P.70 Updated Ihalt max to 120uA
P.78 Added reset pulse timing
P.52 Updated “GDDRAM data and instruction setting needed to be sent again after exit deep
sleep mode” to “DDRAM data needed to be sent again after exit deep sleep mode”
P.94 Added Chip tray information
Advanced information
P.33, 48 Remove HVCI bit in R12h
P.48, 87 Corrected R12h code to 2999h
P.33, 51 Corrected R15h POR to B010h
P.35 Correct read ID code from 1919h to 9919h
P.12, 91 Swapped CYN and CYP pins
P.33, 52, 53Add R16 and R17 register
P.57 Add Program voltage range – 14.5 to 15.5
P.57 Added “It is possible to skip step3 and step4” and changed “Step 4-9” to “Step 5-9”
P.34, 54 Added R20h Uniformity settings
P.11 Updated ordering part number as SSD2119Z7
P.73 Removed (/CS) from tr and tf
P.73 Added VCI and Reset pin to diagram
P.74 Removed (/CS) from tr and tf
P.75 Added VCI and Reset pin to diagram
P.78 Updated Fig13-5 as power up sequence for RGB mode
P.87 Added timing to display off sequence
Rev 1.4
P 3/95
Jun 2009
Solomon Systech
Effective
Date
24-Sep-08
06-Oct-08
13-Nov-08
26-Nov-08
16-Dec-08
23-Jan-09
13-Feb-09