SSD1298 Crystalfontz America, Inc.,, SSD1298 Datasheet
SSD1298
Related parts for SSD1298
SSD1298 Summary of contents
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... RGB x 320 TFT LCD Controller Driver integrated Power Circuit, Gate and Source Driver This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com Rev 1.1 P 1/82 SSD1298 SSD1298 with built-in RAM Copyright © 2008 Solomon Systech Limited Mar 2008 ...
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... COMMAND DESCRIPTION...................................................................................... 30 10 GAMMA ADJUSTMENT FUNCTION ....................................................................... 55 11 MAXIMUM RATINGS................................................................................................ CHARACTERISTICS.......................................................................................... CHARACTERISTICS.......................................................................................... 64 14 GDDRAM ADDRESS................................................................................................ 69 15 INTERFACE MAPPING ............................................................................................ 70 16 DISPLAY SETTING SEQUENCE ............................................................................. 73 17 POWER SUPPLY BLOCK DIAGRAM...................................................................... 76 18 SSD1298 OUTPUT VOLTAGE RELATIONSHIP ..................................................... 77 19 PACKAGE INFORMATION ...................................................................................... 81 Solomon Systech Mar 2008 P 2/82 Rev 1.1 SSD1298 ...
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... TABLES Table 3-1 – Ordering Information......................................................................................................... 7 Table 4-2 - SSD1298 Bump Pad Coordinate (Bump Center)............................................................. 10 Table 5-1: Power Supply Pins ............................................................................................................ 19 Table 5-2 - Interface Logic Pins ......................................................................................................... 21 Table 5-3: Mode Selection Pins.......................................................................................................... 22 Table 5-4: Driver Output Pins............................................................................................................. 23 Table 5-5: Miscellaneous Pins ............................................................................................................ 23 Table 6-1 - Data bus selection modes ................................................................................................. 25 Table 7-1 - Command Table ............................................................................................................... 28 Table 8-1 - 3-field interlace driving.................................................................................................... 34 Table 12-1 – ...
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... FIGURES Figure 4-1 - SSD1298 Block Diagram Description.............................................................................. 8 Figure 6-1 – Read Display Data.......................................................................................................... 24 Figure 6-2: 3-wire SPI interface (9 bits) ............................................................................................. 25 Figure 6-3: 4-wire SPI interface (8 bits) ............................................................................................. 26 Figure 8-1 - gate output timing in 3-field interlacing driving............................................................. 34 Figure 8-2 - Line Inversion AC Driver ............................................................................................... 35 Figure 8-3 – OTP circuitry.................................................................................................................. 49 Figure 12-1 –Parallel 6800-series Interface Timing Characteristics .................................................. 64 Figure 12-2 – ...
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... An Integrated Gamma Control Circuit is also included that can be adjusted by software commands to provide maximum flexibility and optimal display quality. SSD1298 can be operated down to 1.4V and provide different power save modes suitable for any portable battery- driven applications requiring long operation period and compact size. ...
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... Support source and gate scan direction control • Programmable gamma correction curve • Built-in Non Volatile Memory for VCOM calibration • Support flexible arrangement of gate circuits on both sides of the glass substrate Solomon Systech Display Size: 240 RGB x 320 Mar 2008 P 6/82 Rev 1.1 SSD1298 ...
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... ORDERING INFORMATION Ordering Part Number SSD1298Z 240 x 3 (720) Rev 1.1 P 7/82 SSD1298 Table 3-1 – Ordering Information Source Gate 320 Mar 2008 Package Form Reference Gold Bump Die Solomon Systech ...
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... BLOCK DIAGRAM Figure 4-1 - SSD1298 VCI VDD regulator VDDIO circuit VCI C1N C1P Booster C2N Circuit C2P C3N C3P CXP CXN CYP CYN OSC VSS/AVSS/ IOGND/VCH Solomon Systech Block Diagram Description G0 to G319 VCOM Regulator Circuit Gamma / Grayscale Voltage Generator Regulator Circuit ...
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... Bump Size 1 Pad Pitch 1 Bump Size 2 Pad Pitch 2 Pin 299 Pad Arrangement (Bump face up) Figure 4-4 - SSD1298 Mar 2008 Diagram showing the die face up. Coordinates are referenced to center of the chip. Coordinate units and size of all alignment marks are in um. All alignment keys do not contain gold ...
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... Table 4-2 - SSD1298 Bump Pad Coordinate (Bump Center) Note: IC material temperature expansion factor is 2.6ppm, customer should take into account during panel design Pad # Pad Name X-pos Y-pos 1 DUMMY -10395.000 -305.620 2 DUMMY -10325.000 -305.620 3 DUMMY -10255.000 -305.620 4 DUMMY -10185.000 -305.620 5 NC -10115.000 -305.620 6 NC -10045 ...
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... VCIM 3325.000 -305.620 198 VCIM 3395.000 -305.620 199 VCIM 3465.000 -305.620 200 VCIX2G 3535.000 -305.620 Rev 1.1 P 11/82 SSD1298 Pad # Pad Name X-pos Y-pos 201 VCIX2G 3605.000 202 VCIX2G 3675.000 203 VCIX2 3745.000 204 VCIX2 3815.000 205 VCIX2 3885.000 206 VCIX2 3955 ...
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... G277 7810.000 168.380 443 G279 7790.000 293.380 444 G281 7770.000 168.380 445 G283 7750.000 293.380 446 G285 7730.000 168.380 447 G287 7710.000 293.380 448 G289 7690.000 168.380 449 G291 7670.000 293.380 450 G293 7650.000 168.380 Mar 2008 P 12/82 Rev 1.1 Y-pos SSD1298 ...
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... S690 6530.000 293.380 497 S689 6510.000 168.380 498 S688 6490.000 293.380 499 S687 6470.000 168.380 500 S686 6450.000 293.380 Rev 1.1 P 13/82 SSD1298 Pad # Pad Name X-pos 501 S685 6430.000 168.380 502 S684 6410.000 293.380 503 S683 6390.000 168.380 504 S682 6370.000 293.380 505 S681 6350 ...
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... S444 1610.000 293.380 743 S443 1590.000 168.380 744 S442 1570.000 293.380 745 S441 1550.000 168.380 746 S440 1530.000 293.380 747 S439 1510.000 168.380 748 S438 1490.000 293.380 749 S437 1470.000 168.380 750 S436 1450.000 293.380 Mar 2008 P 14/82 Rev 1.1 Y-pos SSD1298 ...
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... S390 530.000 293.380 797 S389 510.000 168.380 798 S388 490.000 293.380 799 S387 470.000 168.380 800 S386 450.000 293.380 Rev 1.1 P 15/82 SSD1298 Pad Pad # X-pos Y-pos Name 801 S385 430.000 168.380 802 S384 410.000 293.380 803 S383 390.000 168.380 804 S382 370 ...
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... S144 -4390.000 293.380 1043 S143 -4410.000 168.380 1044 S142 -4430.000 293.380 1045 S141 -4450.000 168.380 1046 S140 -4470.000 293.380 1047 S139 -4490.000 168.380 1048 S138 -4510.000 293.380 1049 S137 -4530.000 168.380 1050 S136 -4550.000 293.380 Mar 2008 P 16/82 Rev 1.1 SSD1298 ...
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... S90 -5470.000 293.380 1097 S89 -5490.000 168.380 1098 S88 -5510.000 293.380 1099 S87 -5530.000 168.380 1100 S86 -5550.000 293.380 Rev 1.1 P 17/82 SSD1298 Pad Pad # X-pos Y-pos Name 1101 S85 -5570.000 168.380 1102 S84 -5590.000 293.380 1103 S83 -5610.000 168.380 1104 S82 -5630 ...
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... G8 -10490.000 168.380 1346 G6 -10510.000 293.380 1347 G4 -10530.000 168.380 1348 G2 -10550.000 293.380 1349 G0 -10570.000 168.380 1350 DUMMY -10590.000 293.380 1351 DUMMY -10610.000 168.380 1352 DUMMY -10630.000 293.380 1353 DUMMY -10650.000 168.380 1354 DUMMY -10670.000 293.380 Mar 2008 P 18/82 Rev 1.1 Y-pos SSD1298 ...
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... C2N C3P Booster capacitor C3N CDUM1P Stabilizing capacitor Rev 1.1 P 19/82 SSD1298 Function System ground pin of the IC. Ground of Grounding for analog circuit. the Power Grounding for logic circuit. Supply Grounding for booster circuit. Booster input voltage pin. Power - Connect to voltage source between 2.5V to 3.6V Supply for Voltage supply pin for analog circuit ...
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... Power for Voltage input pin for logic I/O, connect to system VDD. interface - Connect to voltage source between 1.4V to 3.6V logic pins Power for Internal regular input for logic supply : VCIR=2.5V- interface 3.3V logic pins Description Mar 2008 P 20/82 Rev 1.1 When not in use Open Open - - - - SSD1298 ...
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... SDI I MPU interface SDO O MPU Rev 1.1 P 21/82 SSD1298 Data or command Chip select pin for 6800/8080/SPI interface 6800-system : E (enable signal) Logic 8080-system : RD (read strobe signal) Serial mode : Not used and should be connected to V 68-system : RW (indicates read cycle when High, write cycle when Low) ...
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... SPI 0 18-bit generic (262k colour) + 3-wire SPI 1 6-bit generic D[8:3] (262k colour) + 3-wire SPI 0 18-bits 6800 parallel interface 1 9-bits 6800 parallel interface 0 18-bit 8080 parallel interface 1 9-bit 8080 parallel interface 0 3-wire SPI 1 4-wire SPI Mar 2008 P 22/82 Rev 1.1 When not in use - SSD1298 ...
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... FPC IO TESTB FPC TESTC FPC Rev 1.1 P 23/82 SSD1298 A power supply for the TFT-display common electrode. Gate driver output pins. These pins output V LCD level. Source driver output pins. S(3n) : display Red if BGR = LOW, Blue if BGR = HIGH. S(3n+1) : display Green. S(3n+2) : display Blue if BGR = LOW, Red if BGR = HIGH. ...
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... Solomon Systech input. The E input serves as data latch signal (clock) when low. Please refer to Parallel Interface Timing Diagram of 6800-series n dummy read data read1 Figure 6-1 – Read Display Data , , E and n+1 n+2 data read 3 data read 2 Mar 2008 P 24/82 Rev 1 SSD1298 ...
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... The serial data transfer starts at the falling edge of CSB input and ends at the rising edge of CSB.SDC determinate the data of SDI which is register or data. Rev 1.1 P 25/82 SSD1298 8080 – series Parallel Interface 18/16/9/8-bits 18/16/9/8-bits Status only ...
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... Register 6.2 RGB Interface SSD1298 supports RGB interface. RGB interface unit consists of D[17:0], HSYNC, VSYNC, DOTCLK and OE signals for display moving pictures. When the RGB interface is selected, the display operation is synchronized with external control signals (HSYNC, VSYNC and DOTCLK). Data is written in synchronization with the control signals when DEN is enabled for write operation in order to avoid flicker or tearing effect while updating display data ...
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... HV Buffer Cell and Level Selector to output the required voltage level. 6.10 Liquid Crystal Driver Circuit SSD1298 consists of a 720-output source driver (S0-S719) and a 320-output gate driver (G0-G319). The display image data is latched when 720 bits of data are inputted. The latched data control the source driver and output drive waveforms ...
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... RTN3 RTN2 RTN1 RTN0 VRC2 VRC1 VRC0 VRH3 VRH2 VRH1 VRH0 SCN3 SCN2 SCN1 SCN0 SLP INVVS SSD1298 ...
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... R4Fh (0000h) Note: In R01h, bits REV, BGR, TB, RL, CM will override the corresponding hardware pins settings. Setting R28h as 0x0006 is required before setting R25h and R29h registers. Rev 1.1 P 29/82 SSD1298 Data[17:0] mapping depends on the interface setting WMR4 WMR3 ...
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... IB5 IB4 IB3 IB2 IB6 IB5 IB4 IB3 IB2 Vcom = ”H” V63 V63 : V0 Mar 2008 P 30/82 Rev 1.1 IB1 IB0 ID1 ID0 IB1 IB0 0 1 IB1 IB0 0 OSCEN 0 0 IB1 IB0 1 1 SSD1298 ...
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... MUX[8:0]: Specify number of lines for the LCD driver. MUX[8:0] settings cannot exceed 319. Remark: When using the partial display, the output for non-display area will be minimum voltage. Rev 1.1 P 31/82 SSD1298 Gate scan squence (GD=’0’) G0, G1, G2, G3……G219 (left and right gate interlaced) G0, G2, ……G318, G1, G3, ……G319 ...
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... G318 ` G317 G319 S0 S719 G316 G318 G317 G319 S0 S719 G316 G318 G317 G319 S0 S719 S719 S719 S719 S719 Mar 2008 P 32/82 Rev 1 G317 G319 G1 G3 G317 G319 G1 G3 G317 G319 G1 G3 G317 G319 SSD1298 ...
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... G316 G318 G316 G318 G316 G318 G316 G318 Rev 1.1 P 33/82 SSD1298 G316 G317 G318 G319 S0 S719 G317 G316 G319 G318 S719 G316 G317 G318 G319 S0 S719 ...
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... frame Blank period Field 1 Field 2 Field 3 IB7 IB6 IB5 IB4 IB3 IB2 NW6 NW5 NW4 NW3 NW2 FLD = 0 FLD = Field 1 Mar 2008 P 34/82 Rev 1.1 IB1 IB0 NW1 NW0 SSD1298 ...
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... Figure 8-2 - Line Inversion AC Driver Back porch Frame Inversion 320 line drive Back porch Line Inversion 320 line drive Rev 1.1 P 35/82 SSD1298 N Frame Front porch Back porch 322 335 336 1 N Frame Front porch Back porch 322 335 336 1 Mar 2008 ...
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... Fast write MCU Slow write MCU SSD1298 displaying memory tn is the time when there is No Update of LCD screen from on-chip ram content the time when the LCD screen is updating based on on-chip ram content. e.g. fosc = 510KHz, for 320mux 282us (6 lines), tu =15.06ms (320 lines) ...
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... BT2 BT1 BT0 Rev 1.1 P 37/82 SSD1298 IB10 IB9 IB8 IB7 BT1 BT0 0 DC3 DCT3 DCT2 DCT1 DCT0 Step-up cycle Fline × Fline × Fline × ...
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... Fline = Line frequency fosc = Internal oscillator frequency (~510KHz) AP2 AP1 AP0 Op-amp power Least Small Small to medium Medium Medium to large Large Large to Maximum Maximum ). When the cycle is accelerated, the SS Mar 2008 P 38/82 Rev 1.1 SSD1298 ...
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... Frame Cycle Control (R0Bh) (POR = 5308h) R/W DC IB15 IB14 IB13 IB12 W 1 NO1 NO0 SDT1 SDT0 POR NO[1:0]: Sets amount of non-overlap of the gate output. Gn Gn+1 Rev 1.1 P 39/82 SSD1298 IB10 IB9 IB8 IB7 PT0 VLE2 VLE1 SPT Internal Display Source output Operation Halt GND Operation ...
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... Delay amount of the source output DIV1 DIV0 Division Ratio fosc = internal oscillator frequency, ~510kHz EQ period clock cycle 3 clock cycle 4 clock cycle 5 clock cycle 6 clock cycle 7 clock cycle 8 clock cycle Equalizing period Mar 2008 P 40/82 Rev 1.1 SSD1298 ...
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... For DMode[1:0] = ‘00’ Frame where Fosc = internal oscillator frequency div = Division ratio determined by DIV[1:0] rtn = RTN[3:0] mux = MUX[8:0] vbp = VBP[7:0] vfp = VFT[7:0] for default values of SSD1298 Fosc = ~510KHz, DIV[1:0] = ‘00’, RTN[3: MUX[8:0] = 319, VBP[7: VFP[7: 510 Frame frequency = × + × ...
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... IB6 IB5 IB4 IB3 IB2 Vcom Amplitude VLCD63 x 0.60 VLCD63 x 0.63 VLCD63 x 0.66 : Step = 0.03 : VLCD63 x 0.99 VLCD63 x 1.02 Reference from external variable resistor VLCD63 x 1.05 VLCD63 x 1.08 : Step = 0.03 : VLCD63 x 1.20 VLCD63 x 1.23 Reserved Reserved Mar 2008 P 42/82 Rev 1.1 IB1 IB0 0 1 IB1 IB0 SSD1298 ...
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... The display operation is performed in synchronization with the internal clock signal generated from the internal oscillator and the VSYNC signal. The display data is written in the internal RAM so that the SSD1298 rewrites the data only within the moving picture area and minimize the number of data transfer required for moving picture display. ...
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... Frame _ frequency ( * mux vfp > eed (min − ( vbp mux m DFM1 DFM0 Color mode 1 1 65k color (POR 262k color TY1 TY0 Writing mode 0 0 Type Type vbp ) rtn div ) 240 * mux 1 + arg ins ) ( * rtn fosc Mar 2008 P 44/82 Rev 1.1 SSD1298 ...
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... bit 262k Type 262k Type Remark : x Rev 1.1 P 45/82 SSD1298 1 0 Type C Hardware pins ...
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... IB7 IB6 IB5 IB4 IB3 ID[1:0]="11” Horizontal: increment Vertical: increment 00,00h 13F,EFh 13F,EFh 00,00h 13F,EFh 13F,EFh IB2 IB1 0 0 INVDOT INVDEN INVHS INVVS Mar 2008 P 46/82 Rev 1.1 IB0 0 SSD1298 ...
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... WD[17:0]: Transforms all the GDDRAM data into 18-bit, and writes the data. Format for transforming data into 18-bit depends on the interface used. SSD1298 selects the grayscale level according to the GDDRAM data. After writing data to GDDRAM, address is automatically updated according to AM bit and ID bit. Access to GDDRAM during stand-by ...
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... LCD module. Solomon Systech IB9 IB8 IB7 Operation Index Value R00h 0x0001 R28h 0x0006 R29h 0x80C0 IB6 IB5 IB4 IB3 IB2 IB1 Mar 2008 P 48/82 Rev 1.1 IB0 0 0 SSD1298 ...
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... PKN[52:00]: Gamma micro adjustment register for the negative polarity output PRN[12:00]: Gradient adjustment register for the negative polarity output VRN[14:00]: Adjustment register for the amplification adjustment of the negative polarity output. (For details, see the Section 11 Gamma Adjustment Function). Rev 1.1 P 49/82 SSD1298 Figure 8-3 – OTP circuitry ...
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... IB7 IB6 IB5 IB4 IB3 IB2 IB7 IB6 IB5 IB4 IB3 IB2 Mar 2008 P 50/82 Rev 1.1 IB1 IB0 IB0 0 IB1 IB0 IB1 IB0 SSD1298 ...
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... R20h is to adjust Internal Vcom strength R26h is to adjust Internal Bandgap strength R27h is to adjust Internal VCOMH/VCOML timing R2Eh is to adjust VCOM charge sharing time R2Fh is to adjust Ram speed Rev 1.1 P 51/82 SSD1298 IB12 IB11 IB10 IB9 IB8 SS28 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20 ...
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... RAM address (either increment or decrement, horizontal or vertical, respectively). Setting these bits enables the SSD1298 to write data including image data sequentially without taking the data wrap position into account. The window address area must be made within the GDDRAM address map area. ...
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... Partial Display and Scrolling Function SSD1298 support schrolling and partial display function. The SSD2220 enables to selectively drive two screens at arbitrary positions with the screen-driving position registers (R48h to R4Bh). Only the lines required to display two screens at arbitrary positions are selectively driven. The first screen driving position registers (R48 and R49) specifies the start line (SS18-10) and the end line (SE18-10) for displaying the first screen ...
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... R41h 0000h VL1[8: R42h 0000h VL2[8: RAM Content ROW 127 128 191 192 255 256 319 Solomon Systech Remark Set PT=11 to set non-display to display data’1’ st Define 1 display window Display Mar 2008 P 54/82 Rev 1.1 Non-display area Display area Non-display area SSD1298 ...
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... GAMMA ADJUSTMENT FUNCTION The SSD1298 incorporates gamma adjustment function for the 262,144-color display. Gamma adjustment is implemented by deciding the 8-grayscale levels with angle adjustment and micro adjustment register. Also, angle adjustment and micro adjustment is fixed for each of the internal positive and negative polarity. Set up by the liquid crystal panel’ ...
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... Individual ladder resistors are used for positive and negative polarity. Amplitude adjustment register PKP5 VRP0 VRP1 VINP0 VINP1 VINP2 VINP3 VINP4 VINP5 VINP6 selector VINP7 Mar 2008 P 56/82 Rev 1 V19 V20 : V42 V43 : V54 V55 : V61 V62 V63 SSD1298 ...
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... KVP43 RP41 KVP44 4R RP42 KVP45 RP43 KVP46 RP44 KVP47 RP45 KVP48 5R RP46 0 to 31R VRP1[4:0] VRP1 8R RP47 GND Rev 1.1 P 57/82 SSD1298 VINP0 VRN0 PKP0[2: VINP1 selector PKP1[2: 28R VRHN VINP2 selector PKP2[2: VINP3 selector PKP3[2:0] ...
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... Also, there is an independent resistor on the positive/negative polarities as well as other adjusting resistors. Solomon Systech Amplitude adjustment Grayscale Number Mar 2008 P 58/82 Micro adjustment Grayscale Number Rev 1.1 SSD1298 ...
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... V20+(V8-V20)*(14/24) V14 V20+(V8-V20)*(12/24) V15 V20+(V8-V20)*(10/24) V16 V20+(V8-V20)*(8/24) V17 V20+(V8-V20)*(6/24) V18 V20+(V8-V20)*(4/24) V19 V20+(V8-V20)*(2/24) V20 VINP(N)3 V21 V43+(V20-V43)*(22/23) Rev 1.1 P 59/82 SSD1298 VRP(N)0 Resistance 0000 0R 0001 2R 0010 4R : Step = 2R : 1110 28R 1111 30R Registor PKN[2:0] VINP4 VINP5 ...
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... PKP4[2:0] = “100” PKP4[2:0] = “101” PKP4[2:0] = “110” PKP4[2:0] = “111” PKP5[2:0] = “000” PKP5[2:0] = “001” PKP5[2:0] = “010” PKP5[2:0] = “011” VINP6 PKP5[2:0] = “100” PKP5[2:0] = “101” PKP5[2:0] = “110” PKP5[2:0] = “111” -- VINP7 Mar 2008 P 60/82 Rev 1.1 SSD1298 ...
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... VLCD63 - ΔV x (VRN0 + 115R + VRHN + VRLN) / SUMRN VLCD63 - ΔV x (VRN0 + 120R + VRHN + VRLN) / SUMRN KVN49 SUMRN: Total of the negative polarity ladder resistance = 128R + VRHN + VRLN + VRN0 + VRN1 ΔV: Voltage difference between VLCD63 and of GND. Rev 1.1 P 61/82 SSD1298 Formula Micr0-adjusting rgister Mar 2008 Reference voltage -- VINN0 PKN0[2:0] = “ ...
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... C = 1.65 to 3.6V -40 to 85°C) DDIO A Min Typ Max 1.4 - 3.6 2.5 - 3.6 2.5 or VDDIO - 3.6 whichever is higher - 0 +0 CIM - - 0.9* VDDIO - VDDIO 0 - 0.1*VDDIO V 0.8*VDDIO - VDDIO 0 - 0.2*VDDIO - Mar 2008 P 62/82 Rev 1.1 Unit μA μA μA SSD1298 ...
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... Display current for 8 color I (8 color) dp mode I Sleep mode current slp Remark: Ivci(total) = Ivci + Ivcir Rev 1.1 P 63/82 SSD1298 Vddi1o = 1.8V, Vci = Ivdd 2.8V. 5x/-5x booster ratio. Full color current consumption, without Ivci panel loading Current consumption for Ivdd 8 color partial display, Ivci without panel loading ...
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... DHW Valid Data t ACC Valid Data Figure 12-1 –Parallel 6800-series Interface Timing Characteristics Min Typ Max 100 - - 1000 - - 250 - - 100 - - 500 - - 500 - - - - PWCS Mar 2008 P 64/82 Rev 1.1 Unit SSD1298 ...
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... D0~D17 Read Cycle D0~D17 Figure 12-2 –Parallel 8080-series Interface Timing Characteristics Rev 1.1 SSD1298 Table 12-2 – Parallel 8080 Timing Characteristics PWCS L t DSW Valid Data PWCS L t ACC Valid Data P 65/82 Mar 2008 Min Typ Max 100 - - 1000 ...
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... CLKL t CLKH DHW DSW Valid Data Figure 12-3 – 4 wire Serial Timing Characteristics Min Typ Max Unit MHz - - CSH Mar 2008 P 66/82 Rev 1.1 SSD1298 ...
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... DS t Data hold Time DH t Reset pulse width RES Note: External clock source must be provided to DOTCLK pin of SSD1298. The driver will not operate in absence of the clocking signal. Rev 1.1 P 67/82 SSD1298 Table 12-4 - RGB Timing Characteristics Figure 0-4 – RGB Timing Characteristics Mar 2008 Min ...
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... Solomon Systech Figure 12-5 - Power Up Sequence Mar 2008 P 68/82 Rev 1.1 SSD1298 ...
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... G316 G3 013CH, 0000H G317 G2 013DH, 0000H G318 G1 013EH, 0000H G319 G0 013FH, 0000H Horizontal address 0 Remark : The address is in 00xxH,0yyyH format, where yyy is the vertical address and xx is the horizontal address Rev 1.1 P 69/82 SSD1298 GDDRAM ADDRESS ...
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... Read 8-bit parameters or status* 0 Write 8-bit command 0 Write 8-bit display data 0 Read 8-bit command 0 Read 8-bit parameters or status* 0 Write 8-bit command 0 Write 18-bit display data 0 Read 8-bit command 0 Read 8-bit parameters or status* 0 Write 8-bit command 0 Write 9-bit display data Rev 1.1 SSD1298 ...
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... D[17: D[8: D[17: Mar 2008 /RD /CS D/C SSD1298 /WR D[17:0] D/C /CS Operation 0 0 Read 8-bit command 1 0 Read 8-bit parameters or status Write 8-bit command 1 0 Write 16-bit display data 0 0 Read 8-bit command 1 0 Read 8-bit parameters or status* ...
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... BB5 BB4 BB3 BB2 BB1 BB0 GG2 GG1 GG0 - - RR5 RR4 RR3 RR2 RR1 RR0 - - GG5 GG4 GG3 GG2 GG1 GG0 BB5 BB4 BB3 BB2 BB1 BB0 Mar 2008 P 72/82 Rev 1 IB1 IB0 x IB1 IB0 SSD1298 ...
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... DISPLAY SETTING SEQUENCE 14.1 Display ON Sequence Rev 1.1 P 73/82 SSD1298 Power supply setting Set R07h at 0021h GON = 1 DTE = 0 D[1: Set R00h at 0001h Set R07h at 0023h GON = 1 DTE = 0 D[1: Set R10h at 0000h Exit sleep mode Wait 30ms Set R07h at 0033h GON = 1 DTE = 1 D[1: Entry Mode setting (R11h) ...
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... VCIX2 discharged before VCI/VDDIO are turned off. Solomon Systech Display ON Set R07h at 0000h Halt the operation Set R00h at 0000h Turn off oscillator Set R10h at 0001h Enter sleep mode Remove power from V , then remove V CI Display OFF V DDIO, CIR Mar 2008 P 74/82 Rev 1.1 SSD1298 ...
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... Sleep Mode Display Sequence Rev 1.1 P 75/82 SSD1298 Display ON Set R10h at 0001h Set R07h at 0000h Sleeping Release from Sleep Set R10h at 0000h Display ON Mar 2008 Ivci = 66uA Solomon Systech ...
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... COMH COML Regulator Circuit & VCOM Generator Circuit VLCD63 Regulator Circuit Gate Driver Generator System Interface / Control Logic V LCD63 Source driver Gamma / Switches Grayscale Network Voltage Generator Data Latches GDDRAM OSC / Address Timing Counter Mar 2008 P 76/82 Rev 1.1 VCOM SSD1298 ...
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... SSD1298 OUTPUT VOLTAGE RELATIONSHIP VCOMH (max 5V) VCI (2.5~3.6V) VSS Note: VGH-VGL<30V p-p Rev 1.1 P 77/82 SSD1298 VLCD63 (max 6V) VCOM amplitude (max 6V) VCOML Mar 2008 VGH (9~18V) VGL (-6~ -15V) Solomon Systech ...
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... Solomon Systech Figure 16-1: Booster Capacitors All capacitors 0.1 ~ 0.22uF (0.22uF for better stability) Figure 16-2 : Filtering and Charge Sharing Capacitors Mandatory requirement on external components for SSD1298 is 13 capacitors. VSS VCIX2, VCIM, VGH, VGL, VCI, VCORE, VCOMH, VCOML C1P/C1N, C2P/C2N, C3P/C3N, CYP/CYN, CXP/CXN Remark: Capacitor for VCIX2 = 2 ...
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... Figure 16-3 – Panel Connection Example G0-G319 Rev 1.1 P 79/82 SSD1298 240RGB x 320 TFT Panel (Cs on Common) 320 720 S0-S719 SSD1298 Mar 2008 Solomon Systech ...
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... VGH VGH VGH VGH VGH VGH DUMMY C3N C3N C3N DUMMY C3P C3P C3P DUMMY C1N C1N C1N C1P C1P C1P C2N C2N C2N C2P C2P C2P CSVCMN CSVCMN CSVCMN CSVCMP CSVCMP CSVCMP DUMMY DUMMY DUMMY DUMMY DUMMY Rev 1.1 SSD1298 ...
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... PACKAGE INFORMATION 17.1 DIE TRAY DIMENSIONS Rev 1.1 P 81/82 SSD1298 Mar 2008 Solomon Systech ...
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... Hazardous Substance (RoHS) Directive (2002/95/EC)” and China standard “电子信息产品污染控制标识要求 (SJ/T11364-2006)” with control Marking Symbol . Hazardous Substances test report is available upon requested. http://www.solomon-systech.com Solomon Systech Mar 2008 P 82/82 Rev 1.1 SSD1298 ...